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Documentation/devicetree/bindings/clock
include/dt-bindings/clock Expand file tree Collapse file tree 2 files changed +32
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lines changed Original file line number Diff line number Diff line change @@ -53,6 +53,7 @@ properties:
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- renesas,r8a779g0-cpg-mssr # R-Car V4H
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- renesas,r8a779h0-cpg-mssr # R-Car V4M
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- renesas,r9a09g077-cpg-mssr # RZ/T2H
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+ - renesas,r9a09g087-cpg-mssr # RZ/N2H
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reg :
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minItems : 1
@@ -112,7 +113,9 @@ allOf:
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properties :
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compatible :
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contains :
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- const : renesas,r9a09g077-cpg-mssr
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+ enum :
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+ - renesas,r9a09g077-cpg-mssr
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+ - renesas,r9a09g087-cpg-mssr
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then :
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properties :
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reg :
Original file line number Diff line number Diff line change
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+ /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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+ *
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+ * Copyright (C) 2025 Renesas Electronics Corp.
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+ */
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+
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+ #ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__
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+ #define __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__
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+
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+ #include <dt-bindings/clock/renesas-cpg-mssr.h>
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+
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+ /* R9A09G087 CPG Core Clocks */
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+ #define R9A09G087_CLK_CA55C0 0
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+ #define R9A09G087_CLK_CA55C1 1
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+ #define R9A09G087_CLK_CA55C2 2
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+ #define R9A09G087_CLK_CA55C3 3
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+ #define R9A09G087_CLK_CA55S 4
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+ #define R9A09G087_CLK_CR52_CPU0 5
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+ #define R9A09G087_CLK_CR52_CPU1 6
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+ #define R9A09G087_CLK_CKIO 7
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+ #define R9A09G087_CLK_PCLKAH 8
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+ #define R9A09G087_CLK_PCLKAM 9
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+ #define R9A09G087_CLK_PCLKAL 10
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+ #define R9A09G087_CLK_PCLKGPTL 11
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+ #define R9A09G087_CLK_PCLKH 12
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+ #define R9A09G087_CLK_PCLKM 13
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+ #define R9A09G087_CLK_PCLKL 14
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+
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+ #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */
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