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riscv: dts: sophgo: sg2044: add PCIe device support for SG2044
Add PCIe device node for SG2044 and configuration for Sophgo SRD3-10. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Inochi Amaoto <[email protected]> Signed-off-by: Chen Wang <[email protected]> Signed-off-by: Chen Wang <[email protected]>
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‎arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts

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status = "okay";
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};
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&pcie0 {
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bus-range = <0x00 0xff>;
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linux,pci-domain = <1>;
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status = "okay";
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};
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&pcie1 {
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bus-range = <0x00 0xff>;
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linux,pci-domain = <0>;
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status = "okay";
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};
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&pcie2 {
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bus-range = <0x00 0xff>;
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linux,pci-domain = <3>;
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status = "okay";
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};
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&pcie3 {
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bus-range = <0x00 0xff>;
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linux,pci-domain = <2>;
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status = "okay";
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};
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&pcie4 {
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bus-range = <0x00 0xff>;
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linux,pci-domain = <4>;
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status = "okay";
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};
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&pwm {
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status = "okay";
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};

‎arch/riscv/boot/dts/sophgo/sg2044.dtsi

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@@ -32,6 +32,181 @@
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#size-cells = <2>;
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ranges;
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pcie0: pcie@6c00000000 {
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compatible = "sophgo,sg2044-pcie";
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reg = <0x6c 0x00000000 0x0 0x00001000>,
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<0x6c 0x00300000 0x0 0x00004000>,
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<0x48 0x00000000 0x0 0x00001000>,
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<0x6c 0x000c0000 0x0 0x00001000>;
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reg-names = "dbi", "atu", "config", "app";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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clocks = <&clk CLK_GATE_PCIE_1G>;
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clock-names = "core";
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device_type = "pci";
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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<0 0 0 2 &pcie_intc0 1>,
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<0 0 0 3 &pcie_intc0 2>,
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<0 0 0 4 &pcie_intc0 3>;
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msi-parent = <&msi>;
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ranges = <0x01000000 0x0 0x00000000 0x48 0x10000000 0x0 0x00200000>,
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<0x42000000 0x0 0x10000000 0x0 0x10000000 0x0 0x04000000>,
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<0x02000000 0x0 0x14000000 0x0 0x14000000 0x0 0x04000000>,
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<0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>,
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<0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>;
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status = "disabled";
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pcie_intc0: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-parent = <&intc>;
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interrupts = <65 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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};
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};
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pcie1: pcie@6c00400000 {
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compatible = "sophgo,sg2044-pcie";
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reg = <0x6c 0x00400000 0x0 0x00001000>,
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<0x6c 0x00700000 0x0 0x00004000>,
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<0x40 0x00000000 0x0 0x00001000>,
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<0x6c 0x00780000 0x0 0x00001000>;
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reg-names = "dbi", "atu", "config", "app";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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clocks = <&clk CLK_GATE_PCIE_1G>;
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clock-names = "core";
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device_type = "pci";
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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<0 0 0 2 &pcie_intc1 1>,
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<0 0 0 3 &pcie_intc1 2>,
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<0 0 0 4 &pcie_intc1 3>;
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msi-parent = <&msi>;
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ranges = <0x01000000 0x0 0x00000000 0x40 0x10000000 0x0 0x00200000>,
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<0x42000000 0x0 0x00000000 0x0 0x00000000 0x0 0x04000000>,
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<0x02000000 0x0 0x04000000 0x0 0x04000000 0x0 0x04000000>,
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<0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>,
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<0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>;
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status = "disabled";
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pcie_intc1: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-parent = <&intc>;
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interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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};
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};
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pcie2: pcie@6c04000000 {
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compatible = "sophgo,sg2044-pcie";
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reg = <0x6c 0x04000000 0x0 0x00001000>,
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<0x6c 0x04300000 0x0 0x00004000>,
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<0x58 0x00000000 0x0 0x00001000>,
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<0x6c 0x040c0000 0x0 0x00001000>;
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reg-names = "dbi", "atu", "config", "app";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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clocks = <&clk CLK_GATE_PCIE_1G>;
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clock-names = "core";
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device_type = "pci";
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc2 0>,
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<0 0 0 2 &pcie_intc2 1>,
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<0 0 0 3 &pcie_intc2 2>,
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<0 0 0 4 &pcie_intc2 3>;
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msi-parent = <&msi>;
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ranges = <0x01000000 0x0 0x00000000 0x58 0x10000000 0x0 0x00200000>,
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<0x42000000 0x0 0x30000000 0x0 0x30000000 0x0 0x04000000>,
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<0x02000000 0x0 0x34000000 0x0 0x34000000 0x0 0x04000000>,
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<0x43000000 0x5a 0x00000000 0x5a 0x00000000 0x2 0x00000000>,
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<0x03000000 0x59 0x00000000 0x59 0x00000000 0x1 0x00000000>;
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status = "disabled";
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pcie_intc2: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-parent = <&intc>;
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interrupts = <74 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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};
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};
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pcie3: pcie@6c04400000 {
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compatible = "sophgo,sg2044-pcie";
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reg = <0x6c 0x04400000 0x0 0x00001000>,
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<0x6c 0x04700000 0x0 0x00004000>,
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<0x50 0x00000000 0x0 0x00001000>,
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<0x6c 0x04780000 0x0 0x00001000>;
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reg-names = "dbi", "atu", "config", "app";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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clocks = <&clk CLK_GATE_PCIE_1G>;
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clock-names = "core";
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device_type = "pci";
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc3 0>,
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<0 0 0 2 &pcie_intc3 1>,
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<0 0 0 3 &pcie_intc3 2>,
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<0 0 0 4 &pcie_intc3 3>;
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msi-parent = <&msi>;
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ranges = <0x01000000 0x0 0x00000000 0x50 0x10000000 0x0 0x00200000>,
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<0x42000000 0x0 0x20000000 0x0 0x20000000 0x0 0x04000000>,
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<0x02000000 0x0 0x24000000 0x0 0x24000000 0x0 0x04000000>,
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<0x43000000 0x52 0x00000000 0x52 0x00000000 0x2 0x00000000>,
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<0x03000000 0x51 0x00000000 0x51 0x00000000 0x1 0x00000000>;
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status = "disabled";
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pcie_intc3: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-parent = <&intc>;
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interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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};
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};
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pcie4: pcie@6c08400000 {
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compatible = "sophgo,sg2044-pcie";
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reg = <0x6c 0x08400000 0x0 0x00001000>,
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<0x6c 0x08700000 0x0 0x00004000>,
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<0x60 0x00000000 0x0 0x00001000>,
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<0x6c 0x08780000 0x0 0x00001000>;
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reg-names = "dbi", "atu", "config", "app";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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clocks = <&clk CLK_GATE_PCIE_1G>;
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clock-names = "core";
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device_type = "pci";
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc4 0>,
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<0 0 0 2 &pcie_intc4 1>,
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<0 0 0 3 &pcie_intc4 2>,
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<0 0 0 4 &pcie_intc4 3>;
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msi-parent = <&msi>;
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ranges = <0x01000000 0x0 0x00000000 0x60 0x10000000 0x0 0x00200000>,
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<0x42000000 0x0 0x40000000 0x0 0x40000000 0x0 0x04000000>,
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<0x02000000 0x0 0x44000000 0x0 0x44000000 0x0 0x04000000>,
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<0x43000000 0x62 0x00000000 0x62 0x00000000 0x2 0x00000000>,
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<0x03000000 0x61 0x00000000 0x61 0x00000000 0x1 0x00000000>;
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status = "disabled";
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pcie_intc4: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-parent = <&intc>;
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interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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};
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};
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msi: msi-controller@6d50000000 {
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compatible = "sophgo,sg2044-msi";
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reg = <0x6d 0x50000000 0x0 0x800>,

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