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| 1 | +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
| 2 | +%YAML 1.2 |
| 3 | +--- |
| 4 | +$id: http://devicetree.org/schemas/soc/qcom/qcom,sa8255p-geni-se-qup.yaml# |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | + |
| 7 | +title: GENI Serial Engine QUP Wrapper Controller |
| 8 | + |
| 9 | +maintainers: |
| 10 | + - Praveen Talari <[email protected]> |
| 11 | + |
| 12 | +description: |
| 13 | + Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper |
| 14 | + is a programmable module for supporting a wide range of serial interfaces |
| 15 | + like UART, SPI, I2C, I3C, etc. A single QUP module can provide up to 8 Serial |
| 16 | + Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP |
| 17 | + Wrapper controller is modeled as a node with zero or more child nodes each |
| 18 | + representing a serial engine. |
| 19 | + |
| 20 | +properties: |
| 21 | + compatible: |
| 22 | + const: qcom,sa8255p-geni-se-qup |
| 23 | + |
| 24 | + reg: |
| 25 | + description: QUP wrapper common register address and length. |
| 26 | + maxItems: 1 |
| 27 | + |
| 28 | + "#address-cells": |
| 29 | + const: 2 |
| 30 | + |
| 31 | + "#size-cells": |
| 32 | + const: 2 |
| 33 | + |
| 34 | + ranges: true |
| 35 | + |
| 36 | + iommus: |
| 37 | + maxItems: 1 |
| 38 | + |
| 39 | + dma-coherent: true |
| 40 | + |
| 41 | +patternProperties: |
| 42 | + "spi@[0-9a-f]+$": |
| 43 | + type: object |
| 44 | + description: GENI serial engine based SPI controller. SPI in master mode |
| 45 | + supports up to 50MHz, up to four chip selects, programmable |
| 46 | + data path from 4 bits to 32 bits and numerous protocol |
| 47 | + variants. |
| 48 | + additionalProperties: true |
| 49 | + |
| 50 | + properties: |
| 51 | + compatible: |
| 52 | + const: qcom,sa8255p-geni-spi |
| 53 | + |
| 54 | + "i2c@[0-9a-f]+$": |
| 55 | + type: object |
| 56 | + description: GENI serial engine based I2C controller. |
| 57 | + additionalProperties: true |
| 58 | + |
| 59 | + properties: |
| 60 | + compatible: |
| 61 | + const: qcom,sa8255p-geni-i2c |
| 62 | + |
| 63 | + "serial@[0-9a-f]+$": |
| 64 | + type: object |
| 65 | + description: GENI Serial Engine based UART Controller. |
| 66 | + additionalProperties: true |
| 67 | + |
| 68 | + properties: |
| 69 | + compatible: |
| 70 | + enum: |
| 71 | + - qcom,sa8255p-geni-uart |
| 72 | + - qcom,sa8255p-geni-debug-uart |
| 73 | + |
| 74 | +required: |
| 75 | + - compatible |
| 76 | + - reg |
| 77 | + - "#address-cells" |
| 78 | + - "#size-cells" |
| 79 | + - ranges |
| 80 | + |
| 81 | +additionalProperties: false |
| 82 | + |
| 83 | +examples: |
| 84 | + - | |
| 85 | + #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 86 | +
|
| 87 | + soc { |
| 88 | + #address-cells = <2>; |
| 89 | + #size-cells = <2>; |
| 90 | +
|
| 91 | + geniqup@9c0000 { |
| 92 | + compatible = "qcom,sa8255p-geni-se-qup"; |
| 93 | + reg = <0 0x9c0000 0 0x6000>; |
| 94 | + #address-cells = <2>; |
| 95 | + #size-cells = <2>; |
| 96 | + ranges; |
| 97 | +
|
| 98 | + serial@990000 { |
| 99 | + compatible = "qcom,sa8255p-geni-uart"; |
| 100 | + reg = <0 0x990000 0 0x4000>; |
| 101 | + interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; |
| 102 | + power-domains = <&scmi0_pd 0>, <&scmi0_dvfs 0>; |
| 103 | + power-domain-names = "power", "perf"; |
| 104 | + }; |
| 105 | + }; |
| 106 | + }; |
| 107 | +... |
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