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apatni7884martinkpetersen
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scsi: ufs: ufs-pci: Fix hibernate state transition for Intel MTL-like host controllers
UFSHCD core disables the UIC completion interrupt when issuing UIC hibernation commands, and re-enables it afterwards if it was enabled to start with, refer ufshcd_uic_pwr_ctrl(). For Intel MTL-like host controllers, accessing the register to re-enable the interrupt disrupts the state transition. Use hibern8_notify variant operation to disable the interrupt during the entire hibernation, thereby preventing the disruption. Fixes: 4049f7a ("scsi: ufs: ufs-pci: Add support for Intel MTL") Cc: [email protected] Signed-off-by: Archana Patni <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Bart Van Assche <[email protected]> Signed-off-by: Martin K. Petersen <[email protected]>
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drivers/ufs/host/ufshcd-pci.c

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@@ -216,6 +216,32 @@ static int ufs_intel_lkf_apply_dev_quirks(struct ufs_hba *hba)
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return ret;
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}
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static void ufs_intel_ctrl_uic_compl(struct ufs_hba *hba, bool enable)
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{
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u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
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if (enable)
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set |= UIC_COMMAND_COMPL;
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else
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set &= ~UIC_COMMAND_COMPL;
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ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
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}
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static void ufs_intel_mtl_h8_notify(struct ufs_hba *hba,
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enum uic_cmd_dme cmd,
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enum ufs_notify_change_status status)
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{
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/*
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* Disable UIC COMPL INTR to prevent access to UFSHCI after
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* checking HCS.UPMCRS
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*/
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if (status == PRE_CHANGE && cmd == UIC_CMD_DME_HIBER_ENTER)
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ufs_intel_ctrl_uic_compl(hba, false);
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if (status == POST_CHANGE && cmd == UIC_CMD_DME_HIBER_EXIT)
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ufs_intel_ctrl_uic_compl(hba, true);
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}
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#define INTEL_ACTIVELTR 0x804
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#define INTEL_IDLELTR 0x808
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@@ -533,6 +559,7 @@ static struct ufs_hba_variant_ops ufs_intel_mtl_hba_vops = {
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.init = ufs_intel_mtl_init,
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.exit = ufs_intel_common_exit,
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.hce_enable_notify = ufs_intel_hce_enable_notify,
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.hibern8_notify = ufs_intel_mtl_h8_notify,
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.link_startup_notify = ufs_intel_link_startup_notify,
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.resume = ufs_intel_resume,
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.device_reset = ufs_intel_device_reset,

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