@@ -386,6 +386,8 @@ DEFINE_CLK_RPMH_VRM(clk6, _a2, "clka6", 2);
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DEFINE_CLK_RPMH_VRM (clk7 , _a2 , "clka7" , 2 );
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DEFINE_CLK_RPMH_VRM (clk8 , _a2 , "clka8" , 2 );
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+ DEFINE_CLK_RPMH_VRM (clk7 , _a4 , "clka7" , 4 );
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+
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DEFINE_CLK_RPMH_VRM (div_clk1 , _div2 , "divclka1" , 2 );
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DEFINE_CLK_RPMH_BCM (ce , "CE0" );
@@ -541,6 +543,29 @@ static const struct clk_rpmh_desc clk_rpmh_sc8180x = {
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.num_clks = ARRAY_SIZE (sc8180x_rpmh_clocks ),
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};
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+ static struct clk_hw * milos_rpmh_clocks [] = {
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+ [RPMH_CXO_CLK ] = & clk_rpmh_bi_tcxo_div4 .hw ,
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+ [RPMH_CXO_CLK_A ] = & clk_rpmh_bi_tcxo_div4_ao .hw ,
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+ [RPMH_LN_BB_CLK2 ] = & clk_rpmh_clk7_a4 .hw ,
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+ [RPMH_LN_BB_CLK2_A ] = & clk_rpmh_clk7_a4_ao .hw ,
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+ /*
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+ * RPMH_LN_BB_CLK3(_A) and RPMH_LN_BB_CLK4(_A) are marked as optional
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+ * downstream, but do not exist in cmd-db on SM7635, so skip them.
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+ */
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+ [RPMH_RF_CLK1 ] = & clk_rpmh_clk1_a1 .hw ,
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+ [RPMH_RF_CLK1_A ] = & clk_rpmh_clk1_a1_ao .hw ,
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+ [RPMH_RF_CLK2 ] = & clk_rpmh_clk2_a1 .hw ,
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+ [RPMH_RF_CLK2_A ] = & clk_rpmh_clk2_a1_ao .hw ,
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+ [RPMH_RF_CLK3 ] = & clk_rpmh_clk3_a1 .hw ,
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+ [RPMH_RF_CLK3_A ] = & clk_rpmh_clk3_a1_ao .hw ,
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+ [RPMH_IPA_CLK ] = & clk_rpmh_ipa .hw ,
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+ };
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+
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+ static const struct clk_rpmh_desc clk_rpmh_milos = {
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+ .clks = milos_rpmh_clocks ,
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+ .num_clks = ARRAY_SIZE (milos_rpmh_clocks ),
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+ };
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+
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static struct clk_hw * sm8250_rpmh_clocks [] = {
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[RPMH_CXO_CLK ] = & clk_rpmh_bi_tcxo_div2 .hw ,
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[RPMH_CXO_CLK_A ] = & clk_rpmh_bi_tcxo_div2_ao .hw ,
@@ -943,6 +968,7 @@ static int clk_rpmh_probe(struct platform_device *pdev)
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}
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static const struct of_device_id clk_rpmh_match_table [] = {
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+ { .compatible = "qcom,milos-rpmh-clk" , .data = & clk_rpmh_milos },
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{ .compatible = "qcom,qcs615-rpmh-clk" , .data = & clk_rpmh_qcs615 },
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{ .compatible = "qcom,qdu1000-rpmh-clk" , .data = & clk_rpmh_qdu1000 },
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{ .compatible = "qcom,sa8775p-rpmh-clk" , .data = & clk_rpmh_sa8775p },
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