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Praveen Talarigregkh
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serial: qcom-geni: move resource initialization to separate function
Enhances code readability and future modifications within the new API. Move the code that handles the actual initialization of resources like clock and ICC paths to a separate function, making the probe function cleaner. Reviewed-by: Bryan O'Donoghue <[email protected]> Signed-off-by: Praveen Talari <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
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drivers/tty/serial/qcom_geni_serial.c

Lines changed: 40 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -1619,6 +1619,43 @@ static struct uart_driver qcom_geni_uart_driver = {
16191619
.nr = GENI_UART_PORTS,
16201620
};
16211621

1622+
static int geni_serial_resource_init(struct qcom_geni_serial_port *port)
1623+
{
1624+
int ret;
1625+
1626+
port->se.clk = devm_clk_get(port->se.dev, "se");
1627+
if (IS_ERR(port->se.clk)) {
1628+
ret = PTR_ERR(port->se.clk);
1629+
dev_err(port->se.dev, "Err getting SE Core clk %d\n", ret);
1630+
return ret;
1631+
}
1632+
1633+
ret = geni_icc_get(&port->se, NULL);
1634+
if (ret)
1635+
return ret;
1636+
1637+
port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
1638+
port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
1639+
1640+
/* Set BW for register access */
1641+
ret = geni_icc_set_bw(&port->se);
1642+
if (ret)
1643+
return ret;
1644+
1645+
ret = devm_pm_opp_set_clkname(port->se.dev, "se");
1646+
if (ret)
1647+
return ret;
1648+
1649+
/* OPP table is optional */
1650+
ret = devm_pm_opp_of_add_table(port->se.dev);
1651+
if (ret && ret != -ENODEV) {
1652+
dev_err(port->se.dev, "invalid OPP table in device tree\n");
1653+
return ret;
1654+
}
1655+
1656+
return 0;
1657+
}
1658+
16221659
static void qcom_geni_serial_pm(struct uart_port *uport,
16231660
unsigned int new_state, unsigned int old_state)
16241661
{
@@ -1739,12 +1776,10 @@ static int qcom_geni_serial_probe(struct platform_device *pdev)
17391776
port->dev_data = data;
17401777
port->se.dev = &pdev->dev;
17411778
port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
1742-
port->se.clk = devm_clk_get(&pdev->dev, "se");
1743-
if (IS_ERR(port->se.clk)) {
1744-
ret = PTR_ERR(port->se.clk);
1745-
dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
1779+
1780+
ret = geni_serial_resource_init(port);
1781+
if (ret)
17461782
return ret;
1747-
}
17481783

17491784
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
17501785
if (!res)
@@ -1764,17 +1799,6 @@ static int qcom_geni_serial_probe(struct platform_device *pdev)
17641799
return -ENOMEM;
17651800
}
17661801

1767-
ret = geni_icc_get(&port->se, NULL);
1768-
if (ret)
1769-
return ret;
1770-
port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
1771-
port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
1772-
1773-
/* Set BW for register access */
1774-
ret = geni_icc_set_bw(&port->se);
1775-
if (ret)
1776-
return ret;
1777-
17781802
port->name = devm_kasprintf(uport->dev, GFP_KERNEL,
17791803
"qcom_geni_serial_%s%d",
17801804
uart_console(uport) ? "console" : "uart", uport->line);
@@ -1796,16 +1820,6 @@ static int qcom_geni_serial_probe(struct platform_device *pdev)
17961820
if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap"))
17971821
port->cts_rts_swap = true;
17981822

1799-
ret = devm_pm_opp_set_clkname(&pdev->dev, "se");
1800-
if (ret)
1801-
return ret;
1802-
/* OPP table is optional */
1803-
ret = devm_pm_opp_of_add_table(&pdev->dev);
1804-
if (ret && ret != -ENODEV) {
1805-
dev_err(&pdev->dev, "invalid OPP table in device tree\n");
1806-
return ret;
1807-
}
1808-
18091823
port->private_data.drv = drv;
18101824
uport->private_data = &port->private_data;
18111825
platform_set_drvdata(pdev, port);

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