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Merge branch 'newsoc/andes' into soc/newsoc
Patches from Ben Zong-You Xie <[email protected]>: The Voyager is a 9.6” x 9.6” Micro ATX form factor development board including Andes QiLai SoC. This patch series adds minimal device tree files for the QiLai SoC and the Voyager board [1]. Now only support basic uart drivers to boot up into a basic console. Other features will be added later. [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/ [2] https://lore.kernel.org/all/[email protected]/ * newsoc/andes: MAINTAINERS: Add entry for Andes SoC riscv: defconfig: enable Andes SoC riscv: dts: andes: add Voyager board device tree riscv: dts: andes: add QiLai SoC device tree dt-bindings: timer: add Andes machine timer dt-bindings: interrupt-controller: add Andes machine-level software interrupt controller dt-bindings: interrupt-controller: add Andes QiLai PLIC dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings riscv: add Andes SoC family Kconfig support
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‎Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/andestech,plicsw.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Andes machine-level software interrupt controller
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description:
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In the Andes platform such as QiLai SoC, the PLIC module is instantiated a
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second time with all interrupt sources tied to zero as the software interrupt
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controller (PLIC_SW). PLIC_SW directly connects to the machine-mode
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inter-processor interrupt lines of CPUs, so RISC-V per-CPU local interrupt
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controller is the parent interrupt controller for PLIC_SW. PLIC_SW can
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generate machine-mode inter-processor interrupts through programming its
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registers.
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maintainers:
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- Ben Zong-You Xie <[email protected]>
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properties:
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compatible:
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items:
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- enum:
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- andestech,qilai-plicsw
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- const: andestech,plicsw
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reg:
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maxItems: 1
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interrupts-extended:
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minItems: 1
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maxItems: 15872
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description:
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Specifies which harts are connected to the PLIC_SW. Each item must points
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to a riscv,cpu-intc node, which has a riscv cpu node as parent.
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additionalProperties: false
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required:
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- compatible
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- reg
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- interrupts-extended
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examples:
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- |
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interrupt-controller@400000 {
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compatible = "andestech,qilai-plicsw", "andestech,plicsw";
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reg = <0x400000 0x400000>;
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interrupts-extended = <&cpu0intc 3>,
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<&cpu1intc 3>,
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<&cpu2intc 3>,
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<&cpu3intc 3>;
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};

‎Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml

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@@ -53,6 +53,7 @@ properties:
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oneOf:
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- items:
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- enum:
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- andestech,qilai-plic
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- renesas,r9a07g043-plic
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- const: andestech,nceplic100
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- items:

‎Documentation/devicetree/bindings/riscv/andes.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/riscv/andes.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Andes SoC-based boards
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maintainers:
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- Ben Zong-You Xie <[email protected]>
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description:
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Andes SoC-based boards
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properties:
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$nodename:
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const: '/'
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compatible:
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oneOf:
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- items:
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- enum:
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- andestech,voyager
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- const: andestech,qilai
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additionalProperties: true

‎Documentation/devicetree/bindings/timer/andestech,plmt0.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/timer/andestech,plmt0.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Andes machine-level timer
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description:
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The Andes machine-level timer device (PLMT0) provides machine-level timer
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functionality for a set of HARTs on a RISC-V platform. It has a single
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fixed-frequency monotonic time counter (MTIME) register and a time compare
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register (MTIMECMP) for each HART connected to the PLMT0. A timer interrupt is
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generated if MTIME >= MTIMECMP.
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maintainers:
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- Ben Zong-You Xie <[email protected]>
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properties:
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compatible:
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items:
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- enum:
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- andestech,qilai-plmt
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- const: andestech,plmt0
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reg:
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maxItems: 1
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interrupts-extended:
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minItems: 1
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maxItems: 32
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description:
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Specifies which harts are connected to the PLMT0. Each item must points
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to a riscv,cpu-intc node, which has a riscv cpu node as parent. The
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PLMT0 supports 1 hart up to 32 harts.
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additionalProperties: false
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required:
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- compatible
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- reg
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- interrupts-extended
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examples:
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- |
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interrupt-controller@100000 {
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compatible = "andestech,qilai-plmt", "andestech,plmt0";
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reg = <0x100000 0x100000>;
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interrupts-extended = <&cpu0intc 7>,
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<&cpu1intc 7>,
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<&cpu2intc 7>,
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<&cpu3intc 7>;
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};

‎MAINTAINERS

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F: include/linux/irqchip/riscv-aplic.h
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F: include/linux/irqchip/riscv-imsic.h
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RISC-V ANDES SoC Support
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M: Ben Zong-You Xie <[email protected]>
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S: Maintained
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T: git: https://github.com/ben717-linux/linux
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F: Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
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F: Documentation/devicetree/bindings/riscv/andes.yaml
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F: Documentation/devicetree/bindings/timer/andestech,plmt0.yaml
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F: arch/riscv/boot/dts/andes/
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RISC-V ARCHITECTURE
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M: Paul Walmsley <[email protected]>
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M: Palmer Dabbelt <[email protected]>

‎arch/riscv/Kconfig.socs

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menu "SoC selection"
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config ARCH_ANDES
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bool "Andes SoCs"
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depends on MMU && !XIP_KERNEL
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select ERRATA_ANDES
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help
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This enables support for Andes SoC platform hardware.
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config ARCH_MICROCHIP_POLARFIRE
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def_bool ARCH_MICROCHIP
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‎arch/riscv/boot/dts/Makefile

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# SPDX-License-Identifier: GPL-2.0
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subdir-y += allwinner
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subdir-y += andes
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subdir-y += canaan
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subdir-y += microchip
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subdir-y += renesas

‎arch/riscv/boot/dts/andes/Makefile

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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_ARCH_ANDES) += qilai-voyager.dtb

‎arch/riscv/boot/dts/andes/qilai-voyager.dts

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// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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* Copyright (C) 2025 Andes Technology Corporation. All rights reserved.
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*/
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#include "qilai.dtsi"
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/ {
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model = "Voyager";
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compatible = "andestech,voyager", "andestech,qilai";
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aliases {
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@400000000 {
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device_type = "memory";
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reg = <0x4 0x00000000 0x4 0x00000000>;
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};
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};
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&uart0 {
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status = "okay";
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};

‎arch/riscv/boot/dts/andes/qilai.dtsi

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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2025 Andes Technology Corporation. All rights reserved.
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <62500000>;
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cpu0: cpu@0 {
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compatible = "andestech,ax45mp", "riscv";
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device_type = "cpu";
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reg = <0>;
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
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"zicntr", "zicsr", "zifencei",
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"zihpm", "xandespmu";
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mmu-type = "riscv,sv39";
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clock-frequency = <100000000>;
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i-cache-size = <0x8000>;
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i-cache-sets = <256>;
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i-cache-line-size = <64>;
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d-cache-size = <0x8000>;
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d-cache-sets = <128>;
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d-cache-line-size = <64>;
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next-level-cache = <&l2_cache>;
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cpu0_intc: interrupt-controller {
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compatible = "andestech,cpu-intc", "riscv,cpu-intc";
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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cpu1: cpu@1 {
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compatible = "andestech,ax45mp", "riscv";
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device_type = "cpu";
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reg = <1>;
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
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"zicntr", "zicsr", "zifencei",
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"zihpm", "xandespmu";
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mmu-type = "riscv,sv39";
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clock-frequency = <100000000>;
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i-cache-size = <0x8000>;
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i-cache-sets = <256>;
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i-cache-line-size = <64>;
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d-cache-size = <0x8000>;
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d-cache-sets = <128>;
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d-cache-line-size = <64>;
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next-level-cache = <&l2_cache>;
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cpu1_intc: interrupt-controller {
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compatible = "andestech,cpu-intc",
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"riscv,cpu-intc";
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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cpu2: cpu@2 {
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compatible = "andestech,ax45mp", "riscv";
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device_type = "cpu";
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reg = <2>;
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
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"zicntr", "zicsr", "zifencei",
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"zihpm", "xandespmu";
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mmu-type = "riscv,sv39";
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clock-frequency = <100000000>;
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i-cache-size = <0x8000>;
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i-cache-sets = <256>;
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i-cache-line-size = <64>;
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d-cache-size = <0x8000>;
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d-cache-sets = <128>;
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d-cache-line-size = <64>;
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next-level-cache = <&l2_cache>;
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cpu2_intc: interrupt-controller {
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compatible = "andestech,cpu-intc",
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"riscv,cpu-intc";
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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cpu3: cpu@3 {
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compatible = "andestech,ax45mp", "riscv";
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device_type = "cpu";
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reg = <3>;
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
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"zicntr", "zicsr", "zifencei",
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"zihpm", "xandespmu";
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mmu-type = "riscv,sv39";
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clock-frequency = <100000000>;
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i-cache-size = <0x8000>;
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i-cache-sets = <256>;
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i-cache-line-size = <64>;
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d-cache-size = <0x8000>;
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d-cache-sets = <128>;
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d-cache-line-size = <64>;
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next-level-cache = <&l2_cache>;
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cpu3_intc: interrupt-controller {
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compatible = "andestech,cpu-intc",
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"riscv,cpu-intc";
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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};
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soc {
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compatible = "simple-bus";
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ranges;
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interrupt-parent = <&plic>;
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#address-cells = <2>;
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#size-cells = <2>;
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plmt: timer@100000 {
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compatible = "andestech,qilai-plmt", "andestech,plmt0";
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reg = <0x0 0x00100000 0x0 0x100000>;
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interrupts-extended = <&cpu0_intc 7>,
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<&cpu1_intc 7>,
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<&cpu2_intc 7>,
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<&cpu3_intc 7>;
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};
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l2_cache: cache-controller@200000 {
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compatible = "andestech,qilai-ax45mp-cache",
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"andestech,ax45mp-cache", "cache";
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reg = <0x0 0x00200000 0x0 0x100000>;
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interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
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cache-line-size = <64>;
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cache-level = <2>;
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cache-sets = <2048>;
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cache-size = <0x200000>;
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cache-unified;
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};
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plic_sw: interrupt-controller@400000 {
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compatible = "andestech,qilai-plicsw",
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"andestech,plicsw";
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reg = <0x0 0x00400000 0x0 0x400000>;
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interrupts-extended = <&cpu0_intc 3>,
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<&cpu1_intc 3>,
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<&cpu2_intc 3>,
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<&cpu3_intc 3>;
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};
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plic: interrupt-controller@2000000 {
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compatible = "andestech,qilai-plic",
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"andestech,nceplic100";
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reg = <0x0 0x02000000 0x0 0x2000000>;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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interrupt-controller;
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interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
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<&cpu1_intc 11>, <&cpu1_intc 9>,
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<&cpu2_intc 11>, <&cpu2_intc 9>,
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<&cpu3_intc 11>, <&cpu3_intc 9>;
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riscv,ndev = <71>;
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};
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uart0: serial@30300000 {
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compatible = "andestech,uart16550", "ns16550a";
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reg = <0x0 0x30300000 0x0 0x100000>;
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interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <50000000>;
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reg-offset = <32>;
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reg-shift = <2>;
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reg-io-width = <4>;
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no-loopback-test;
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};
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};
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};

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