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12 | 12 | #define ADI_AXI_COMMON_H_
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13 | 13 |
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14 | 14 | #define ADI_AXI_REG_VERSION 0x0000
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| 15 | +#define ADI_AXI_REG_FPGA_INFO 0x001C |
15 | 16 |
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16 | 17 | #define ADI_AXI_PCORE_VER(major, minor, patch) \
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17 | 18 | (((major) << 16) | ((minor) << 8) | (patch))
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20 | 21 | #define ADI_AXI_PCORE_VER_MINOR(version) (((version) >> 8) & 0xff)
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21 | 22 | #define ADI_AXI_PCORE_VER_PATCH(version) ((version) & 0xff)
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22 | 23 |
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| 24 | +#define ADI_AXI_INFO_FPGA_TECH(info) (((info) >> 24) & 0xff) |
| 25 | +#define ADI_AXI_INFO_FPGA_FAMILY(info) (((info) >> 16) & 0xff) |
| 26 | +#define ADI_AXI_INFO_FPGA_SPEED_GRADE(info) (((info) >> 8) & 0xff) |
| 27 | + |
| 28 | +enum adi_axi_fpga_technology { |
| 29 | + ADI_AXI_FPGA_TECH_UNKNOWN = 0, |
| 30 | + ADI_AXI_FPGA_TECH_SERIES7, |
| 31 | + ADI_AXI_FPGA_TECH_ULTRASCALE, |
| 32 | + ADI_AXI_FPGA_TECH_ULTRASCALE_PLUS, |
| 33 | +}; |
| 34 | + |
| 35 | +enum adi_axi_fpga_family { |
| 36 | + ADI_AXI_FPGA_FAMILY_UNKNOWN = 0, |
| 37 | + ADI_AXI_FPGA_FAMILY_ARTIX, |
| 38 | + ADI_AXI_FPGA_FAMILY_KINTEX, |
| 39 | + ADI_AXI_FPGA_FAMILY_VIRTEX, |
| 40 | + ADI_AXI_FPGA_FAMILY_ZYNQ, |
| 41 | +}; |
| 42 | + |
| 43 | +enum adi_axi_fpga_speed_grade { |
| 44 | + ADI_AXI_FPGA_SPEED_UNKNOWN = 0, |
| 45 | + ADI_AXI_FPGA_SPEED_1 = 10, |
| 46 | + ADI_AXI_FPGA_SPEED_1L = 11, |
| 47 | + ADI_AXI_FPGA_SPEED_1H = 12, |
| 48 | + ADI_AXI_FPGA_SPEED_1HV = 13, |
| 49 | + ADI_AXI_FPGA_SPEED_1LV = 14, |
| 50 | + ADI_AXI_FPGA_SPEED_2 = 20, |
| 51 | + ADI_AXI_FPGA_SPEED_2L = 21, |
| 52 | + ADI_AXI_FPGA_SPEED_2LV = 22, |
| 53 | + ADI_AXI_FPGA_SPEED_3 = 30, |
| 54 | +}; |
| 55 | + |
23 | 56 | #endif /* ADI_AXI_COMMON_H_ */
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