36
36
37
37
/*
38
38
* PG0 is HW controlled, so doesn't have a corresponding power well control knob
39
- * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2
40
- */
41
- #define SKL_PW_CTL_IDX_TO_PG (pw_idx ) \
42
- ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
43
- /*
44
- * PG0 is HW controlled, so doesn't have a corresponding power well control knob
45
- * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4
39
+ *
40
+ * {ICL,SKL}_DISP_PW1_IDX..{ICL,SKL}_DISP_PW4_IDX -> PG1..PG4
46
41
*/
47
- #define ICL_PW_CTL_IDX_TO_PG (pw_idx ) \
48
- ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
42
+ static enum skl_power_gate pw_idx_to_pg (struct intel_display * display , int pw_idx )
43
+ {
44
+ int pw1_idx = DISPLAY_VER (display ) >= 11 ? ICL_PW_CTL_IDX_PW_1 : SKL_PW_CTL_IDX_PW_1 ;
45
+
46
+ return pw_idx - pw1_idx + SKL_PG1 ;
47
+ }
49
48
50
49
struct i915_power_well_regs {
51
50
i915_reg_t bios ;
@@ -363,8 +362,7 @@ static void hsw_power_well_enable(struct intel_display *display,
363
362
if (power_well -> desc -> has_fuses ) {
364
363
enum skl_power_gate pg ;
365
364
366
- pg = DISPLAY_VER (display ) >= 11 ? ICL_PW_CTL_IDX_TO_PG (pw_idx ) :
367
- SKL_PW_CTL_IDX_TO_PG (pw_idx );
365
+ pg = pw_idx_to_pg (display , pw_idx );
368
366
369
367
/* Wa_16013190616:adlp */
370
368
if (display -> platform .alderlake_p && pg == SKL_PG1 )
@@ -388,8 +386,8 @@ static void hsw_power_well_enable(struct intel_display *display,
388
386
if (power_well -> desc -> has_fuses ) {
389
387
enum skl_power_gate pg ;
390
388
391
- pg = DISPLAY_VER (display ) >= 11 ? ICL_PW_CTL_IDX_TO_PG ( pw_idx ) :
392
- SKL_PW_CTL_IDX_TO_PG ( pw_idx );
389
+ pg = pw_idx_to_pg (display , pw_idx );
390
+
393
391
gen9_wait_for_power_well_fuses (display , pg );
394
392
}
395
393
0 commit comments