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Merge tag 'loongarch-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
Pull LoongArch updates from Huacai Chen: - Complete KSave registers definition - Support the mem=<size> kernel parameter - Support BPF dynamic modification & trampoline - Add MMC/SDIO controller nodes in dts - Some bug fixes and other small changes * tag 'loongarch-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson: LoongArch: vDSO: Remove -nostdlib complier flag LoongArch: dts: Add eMMC/SDIO controller support to Loongson-2K2000 LoongArch: dts: Add SDIO controller support to Loongson-2K1000 LoongArch: dts: Add SDIO controller support to Loongson-2K0500 LoongArch: BPF: Set bpf_jit_bypass_spec_v1/v4() LoongArch: BPF: Fix the tailcall hierarchy LoongArch: BPF: Fix jump offset calculation in tailcall LoongArch: BPF: Add struct ops support for trampoline LoongArch: BPF: Add basic bpf trampoline support LoongArch: BPF: Add dynamic code modification support LoongArch: BPF: Rename and refactor validate_code() LoongArch: Add larch_insn_gen_{beq,bne} helpers LoongArch: Don't use %pK through printk() in unwinder LoongArch: Avoid in-place string operation on FDT content LoongArch: Support mem=<size> kernel parameter LoongArch: Make relocate_new_kernel_size be a .quad value LoongArch: Complete KSave registers definition
2 parents 6e64f45 + d35ec48 commit 83affac

16 files changed

+841
-89
lines changed

‎arch/loongarch/boot/dts/loongson-2k0500-ref.dts

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -41,6 +41,15 @@
4141
};
4242
};
4343

44+
&apbdma3 {
45+
status = "okay";
46+
};
47+
48+
&mmc0 {
49+
status = "okay";
50+
bus-width = <4>;
51+
};
52+
4453
&gmac0 {
4554
status = "okay";
4655

‎arch/loongarch/boot/dts/loongson-2k0500.dtsi

Lines changed: 26 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -104,7 +104,7 @@
104104
status = "disabled";
105105
};
106106

107-
dma-controller@1fe10c20 {
107+
apbdma2: dma-controller@1fe10c20 {
108108
compatible = "loongson,ls2k0500-apbdma", "loongson,ls2k1000-apbdma";
109109
reg = <0 0x1fe10c20 0 0x8>;
110110
interrupt-parent = <&eiointc>;
@@ -114,7 +114,7 @@
114114
status = "disabled";
115115
};
116116

117-
dma-controller@1fe10c30 {
117+
apbdma3: dma-controller@1fe10c30 {
118118
compatible = "loongson,ls2k0500-apbdma", "loongson,ls2k1000-apbdma";
119119
reg = <0 0x1fe10c30 0 0x8>;
120120
interrupt-parent = <&eiointc>;
@@ -437,6 +437,30 @@
437437
status = "disabled";
438438
};
439439

440+
mmc0: mmc@1ff64000 {
441+
compatible = "loongson,ls2k0500-mmc";
442+
reg = <0 0x1ff64000 0 0x2000>,
443+
<0 0x1fe10100 0 0x4>;
444+
interrupt-parent = <&eiointc>;
445+
interrupts = <57>;
446+
dmas = <&apbdma3 0>;
447+
dma-names = "rx-tx";
448+
clocks = <&clk LOONGSON2_APB_CLK>;
449+
status = "disabled";
450+
};
451+
452+
mmc@1ff66000 {
453+
compatible = "loongson,ls2k0500-mmc";
454+
reg = <0 0x1ff66000 0 0x2000>,
455+
<0 0x1fe10100 0 0x4>;
456+
interrupt-parent = <&eiointc>;
457+
interrupts = <58>;
458+
dmas = <&apbdma2 0>;
459+
dma-names = "rx-tx";
460+
clocks = <&clk LOONGSON2_APB_CLK>;
461+
status = "disabled";
462+
};
463+
440464
pmc: power-management@1ff6c000 {
441465
compatible = "loongson,ls2k0500-pmc", "syscon";
442466
reg = <0x0 0x1ff6c000 0x0 0x58>;

‎arch/loongarch/boot/dts/loongson-2k1000-ref.dts

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,19 @@
4848
};
4949
};
5050

51+
&apbdma1 {
52+
status = "okay";
53+
};
54+
55+
&mmc {
56+
status = "okay";
57+
58+
pinctrl-0 = <&sdio_pins_default>;
59+
pinctrl-names = "default";
60+
bus-width = <4>;
61+
cd-gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
62+
};
63+
5164
&gmac0 {
5265
status = "okay";
5366

‎arch/loongarch/boot/dts/loongson-2k1000.dtsi

Lines changed: 18 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -187,14 +187,14 @@
187187
<26 IRQ_TYPE_LEVEL_HIGH>,
188188
<26 IRQ_TYPE_LEVEL_HIGH>,
189189
<26 IRQ_TYPE_LEVEL_HIGH>,
190-
<>,
191-
<26 IRQ_TYPE_LEVEL_HIGH>,
190+
<0 IRQ_TYPE_NONE>,
192191
<26 IRQ_TYPE_LEVEL_HIGH>,
193192
<26 IRQ_TYPE_LEVEL_HIGH>,
194193
<26 IRQ_TYPE_LEVEL_HIGH>,
195194
<26 IRQ_TYPE_LEVEL_HIGH>,
196195
<26 IRQ_TYPE_LEVEL_HIGH>,
197196
<26 IRQ_TYPE_LEVEL_HIGH>,
197+
<26 IRQ_TYPE_NONE>,
198198
<26 IRQ_TYPE_LEVEL_HIGH>,
199199
<26 IRQ_TYPE_LEVEL_HIGH>,
200200
<26 IRQ_TYPE_LEVEL_HIGH>,
@@ -209,13 +209,13 @@
209209
<27 IRQ_TYPE_LEVEL_HIGH>,
210210
<27 IRQ_TYPE_LEVEL_HIGH>,
211211
<27 IRQ_TYPE_LEVEL_HIGH>,
212-
<>,
212+
<0 IRQ_TYPE_NONE>,
213213
<27 IRQ_TYPE_LEVEL_HIGH>,
214214
<27 IRQ_TYPE_LEVEL_HIGH>,
215215
<27 IRQ_TYPE_LEVEL_HIGH>,
216216
<27 IRQ_TYPE_LEVEL_HIGH>,
217-
<>,
218-
<>,
217+
<0 IRQ_TYPE_NONE>,
218+
<0 IRQ_TYPE_NONE>,
219219
<27 IRQ_TYPE_LEVEL_HIGH>,
220220
<27 IRQ_TYPE_LEVEL_HIGH>,
221221
<27 IRQ_TYPE_LEVEL_HIGH>,
@@ -256,7 +256,7 @@
256256
status = "disabled";
257257
};
258258

259-
dma-controller@1fe00c10 {
259+
apbdma1: dma-controller@1fe00c10 {
260260
compatible = "loongson,ls2k1000-apbdma";
261261
reg = <0x0 0x1fe00c10 0x0 0x8>;
262262
interrupt-parent = <&liointc1>;
@@ -405,6 +405,18 @@
405405
status = "disabled";
406406
};
407407

408+
mmc: mmc@1fe2c000 {
409+
compatible = "loongson,ls2k1000-mmc";
410+
reg = <0 0x1fe2c000 0 0x68>,
411+
<0 0x1fe00438 0 0x8>;
412+
interrupt-parent = <&liointc0>;
413+
interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
414+
clocks = <&clk LOONGSON2_APB_CLK>;
415+
dmas = <&apbdma1 0>;
416+
dma-names = "rx-tx";
417+
status = "disabled";
418+
};
419+
408420
spi0: spi@1fff0220 {
409421
compatible = "loongson,ls2k1000-spi";
410422
reg = <0x0 0x1fff0220 0x0 0x10>;

‎arch/loongarch/boot/dts/loongson-2k2000-ref.dts

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,16 @@
3939
};
4040
};
4141

42+
&emmc {
43+
status = "okay";
44+
45+
bus-width = <8>;
46+
cap-mmc-highspeed;
47+
mmc-hs200-1_8v;
48+
no-sd;
49+
no-sdio;
50+
};
51+
4252
&sata {
4353
status = "okay";
4454
};

‎arch/loongarch/boot/dts/loongson-2k2000.dtsi

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -259,6 +259,24 @@
259259
status = "disabled";
260260
};
261261

262+
emmc: mmc@79990000 {
263+
compatible = "loongson,ls2k2000-mmc";
264+
reg = <0x0 0x79990000 0x0 0x1000>;
265+
interrupt-parent = <&pic>;
266+
interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
267+
clocks = <&clk LOONGSON2_EMMC_CLK>;
268+
status = "disabled";
269+
};
270+
271+
mmc@79991000 {
272+
compatible = "loongson,ls2k2000-mmc";
273+
reg = <0x0 0x79991000 0x0 0x1000>;
274+
interrupt-parent = <&pic>;
275+
interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
276+
clocks = <&clk LOONGSON2_EMMC_CLK>;
277+
status = "disabled";
278+
};
279+
262280
pcie@1a000000 {
263281
compatible = "loongson,ls2k-pci";
264282
reg = <0x0 0x1a000000 0x0 0x02000000>,

‎arch/loongarch/include/asm/inst.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -497,6 +497,7 @@ void arch_simulate_insn(union loongarch_instruction insn, struct pt_regs *regs);
497497
int larch_insn_read(void *addr, u32 *insnp);
498498
int larch_insn_write(void *addr, u32 insn);
499499
int larch_insn_patch_text(void *addr, u32 insn);
500+
int larch_insn_text_copy(void *dst, void *src, size_t len);
500501

501502
u32 larch_insn_gen_nop(void);
502503
u32 larch_insn_gen_b(unsigned long pc, unsigned long dest);
@@ -510,6 +511,8 @@ u32 larch_insn_gen_move(enum loongarch_gpr rd, enum loongarch_gpr rj);
510511
u32 larch_insn_gen_lu12iw(enum loongarch_gpr rd, int imm);
511512
u32 larch_insn_gen_lu32id(enum loongarch_gpr rd, int imm);
512513
u32 larch_insn_gen_lu52id(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm);
514+
u32 larch_insn_gen_beq(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm);
515+
u32 larch_insn_gen_bne(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm);
513516
u32 larch_insn_gen_jirl(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm);
514517

515518
static inline bool signed_imm_check(long val, unsigned int bit)

‎arch/loongarch/include/asm/loongarch.h

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -451,6 +451,13 @@
451451
#define LOONGARCH_CSR_KS6 0x36
452452
#define LOONGARCH_CSR_KS7 0x37
453453
#define LOONGARCH_CSR_KS8 0x38
454+
#define LOONGARCH_CSR_KS9 0x39
455+
#define LOONGARCH_CSR_KS10 0x3a
456+
#define LOONGARCH_CSR_KS11 0x3b
457+
#define LOONGARCH_CSR_KS12 0x3c
458+
#define LOONGARCH_CSR_KS13 0x3d
459+
#define LOONGARCH_CSR_KS14 0x3e
460+
#define LOONGARCH_CSR_KS15 0x3f
454461

455462
/* Exception allocated KS0, KS1 and KS2 statically */
456463
#define EXCEPTION_KS0 LOONGARCH_CSR_KS0

‎arch/loongarch/kernel/env.c

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -39,16 +39,19 @@ void __init init_environ(void)
3939

4040
static int __init init_cpu_fullname(void)
4141
{
42-
struct device_node *root;
4342
int cpu, ret;
44-
char *model;
43+
char *cpuname;
44+
const char *model;
45+
struct device_node *root;
4546

4647
/* Parsing cpuname from DTS model property */
4748
root = of_find_node_by_path("/");
48-
ret = of_property_read_string(root, "model", (const char **)&model);
49+
ret = of_property_read_string(root, "model", &model);
50+
if (ret == 0) {
51+
cpuname = kstrdup(model, GFP_KERNEL);
52+
loongson_sysconf.cpuname = strsep(&cpuname, " ");
53+
}
4954
of_node_put(root);
50-
if (ret == 0)
51-
loongson_sysconf.cpuname = strsep(&model, " ");
5255

5356
if (loongson_sysconf.cpuname && !strncmp(loongson_sysconf.cpuname, "Loongson", 8)) {
5457
for (cpu = 0; cpu < NR_CPUS; cpu++)

‎arch/loongarch/kernel/inst.c

Lines changed: 74 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,8 @@
44
*/
55
#include <linux/sizes.h>
66
#include <linux/uaccess.h>
7+
#include <linux/set_memory.h>
8+
#include <linux/stop_machine.h>
79

810
#include <asm/cacheflush.h>
911
#include <asm/inst.h>
@@ -218,6 +220,50 @@ int larch_insn_patch_text(void *addr, u32 insn)
218220
return ret;
219221
}
220222

223+
struct insn_copy {
224+
void *dst;
225+
void *src;
226+
size_t len;
227+
unsigned int cpu;
228+
};
229+
230+
static int text_copy_cb(void *data)
231+
{
232+
int ret = 0;
233+
struct insn_copy *copy = data;
234+
235+
if (smp_processor_id() == copy->cpu) {
236+
ret = copy_to_kernel_nofault(copy->dst, copy->src, copy->len);
237+
if (ret)
238+
pr_err("%s: operation failed\n", __func__);
239+
}
240+
241+
flush_icache_range((unsigned long)copy->dst, (unsigned long)copy->dst + copy->len);
242+
243+
return ret;
244+
}
245+
246+
int larch_insn_text_copy(void *dst, void *src, size_t len)
247+
{
248+
int ret = 0;
249+
size_t start, end;
250+
struct insn_copy copy = {
251+
.dst = dst,
252+
.src = src,
253+
.len = len,
254+
.cpu = smp_processor_id(),
255+
};
256+
257+
start = round_down((size_t)dst, PAGE_SIZE);
258+
end = round_up((size_t)dst + len, PAGE_SIZE);
259+
260+
set_memory_rw(start, (end - start) / PAGE_SIZE);
261+
ret = stop_machine(text_copy_cb, &copy, cpu_online_mask);
262+
set_memory_rox(start, (end - start) / PAGE_SIZE);
263+
264+
return ret;
265+
}
266+
221267
u32 larch_insn_gen_nop(void)
222268
{
223269
return INSN_NOP;
@@ -323,6 +369,34 @@ u32 larch_insn_gen_lu52id(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm)
323369
return insn.word;
324370
}
325371

372+
u32 larch_insn_gen_beq(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm)
373+
{
374+
union loongarch_instruction insn;
375+
376+
if ((imm & 3) || imm < -SZ_128K || imm >= SZ_128K) {
377+
pr_warn("The generated beq instruction is out of range.\n");
378+
return INSN_BREAK;
379+
}
380+
381+
emit_beq(&insn, rj, rd, imm >> 2);
382+
383+
return insn.word;
384+
}
385+
386+
u32 larch_insn_gen_bne(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm)
387+
{
388+
union loongarch_instruction insn;
389+
390+
if ((imm & 3) || imm < -SZ_128K || imm >= SZ_128K) {
391+
pr_warn("The generated bne instruction is out of range.\n");
392+
return INSN_BREAK;
393+
}
394+
395+
emit_bne(&insn, rj, rd, imm >> 2);
396+
397+
return insn.word;
398+
}
399+
326400
u32 larch_insn_gen_jirl(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm)
327401
{
328402
union loongarch_instruction insn;

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