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Lijo Lazaralexdeucher
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drm/amd/pm: Use cached data for min/max clocks
If dpm tables are already populated on SMU v13.0.6 SOCs, use the cached data. Otherwise, fetch values from firmware. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Asad Kamal <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -881,51 +881,51 @@ static int smu_v13_0_6_get_dpm_ultimate_freq(struct smu_context *smu,
881881
enum smu_clk_type clk_type,
882882
uint32_t *min, uint32_t *max)
883883
{
884+
struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
884885
struct smu_table_context *smu_table = &smu->smu_table;
885886
struct PPTable_t *pptable =
886887
(struct PPTable_t *)smu_table->driver_pptable;
887-
uint32_t clock_limit = 0, param;
888+
struct smu_13_0_dpm_table *dpm_table;
889+
uint32_t min_clk, max_clk, param;
888890
int ret = 0, clk_id = 0;
889891

890-
if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
892+
/* Use dpm tables, if data is already fetched */
893+
if (pptable->Init) {
891894
switch (clk_type) {
892895
case SMU_MCLK:
893896
case SMU_UCLK:
894-
if (pptable->Init)
895-
clock_limit = pptable->UclkFrequencyTable[0];
897+
dpm_table = &dpm_context->dpm_tables.uclk_table;
896898
break;
897899
case SMU_GFXCLK:
898900
case SMU_SCLK:
899-
if (pptable->Init)
900-
clock_limit = pptable->MinGfxclkFrequency;
901+
dpm_table = &dpm_context->dpm_tables.gfx_table;
901902
break;
902903
case SMU_SOCCLK:
903-
if (pptable->Init)
904-
clock_limit = pptable->SocclkFrequencyTable[0];
904+
dpm_table = &dpm_context->dpm_tables.soc_table;
905905
break;
906906
case SMU_FCLK:
907-
if (pptable->Init)
908-
clock_limit = pptable->FclkFrequencyTable[0];
907+
dpm_table = &dpm_context->dpm_tables.fclk_table;
909908
break;
910909
case SMU_VCLK:
911-
if (pptable->Init)
912-
clock_limit = pptable->VclkFrequencyTable[0];
910+
dpm_table = &dpm_context->dpm_tables.vclk_table;
913911
break;
914912
case SMU_DCLK:
915-
if (pptable->Init)
916-
clock_limit = pptable->DclkFrequencyTable[0];
913+
dpm_table = &dpm_context->dpm_tables.dclk_table;
917914
break;
918915
default:
919-
break;
916+
return -EINVAL;
920917
}
921918

922-
if (min)
923-
*min = clock_limit;
919+
min_clk = dpm_table->min;
920+
max_clk = dpm_table->max;
924921

922+
if (min)
923+
*min = min_clk;
925924
if (max)
926-
*max = clock_limit;
925+
*max = max_clk;
927926

928-
return 0;
927+
if (min_clk && max_clk)
928+
return 0;
929929
}
930930

931931
if (!(clk_type == SMU_GFXCLK || clk_type == SMU_SCLK)) {

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