@@ -156,7 +156,7 @@ static const struct imx95_blk_ctl_dev_data camblk_dev_data = {
156
156
.clk_reg_offset = 0 ,
157
157
};
158
158
159
- static const struct imx95_blk_ctl_clk_dev_data lvds_clk_dev_data [] = {
159
+ static const struct imx95_blk_ctl_clk_dev_data imx95_lvds_clk_dev_data [] = {
160
160
[IMX95_CLK_DISPMIX_LVDS_PHY_DIV ] = {
161
161
.name = "ldb_phy_div" ,
162
162
.parent_names = (const char * []){ "ldbpll" , },
@@ -213,21 +213,21 @@ static const struct imx95_blk_ctl_clk_dev_data lvds_clk_dev_data[] = {
213
213
},
214
214
};
215
215
216
- static const struct imx95_blk_ctl_dev_data lvds_csr_dev_data = {
217
- .num_clks = ARRAY_SIZE (lvds_clk_dev_data ),
218
- .clk_dev_data = lvds_clk_dev_data ,
216
+ static const struct imx95_blk_ctl_dev_data imx95_lvds_csr_dev_data = {
217
+ .num_clks = ARRAY_SIZE (imx95_lvds_clk_dev_data ),
218
+ .clk_dev_data = imx95_lvds_clk_dev_data ,
219
219
.clk_reg_offset = 0 ,
220
220
};
221
221
222
- static const char * const disp_engine_parents [] = {
222
+ static const char * const imx95_disp_engine_parents [] = {
223
223
"videopll1" , "dsi_pll" , "ldb_pll_div7"
224
224
};
225
225
226
- static const struct imx95_blk_ctl_clk_dev_data dispmix_csr_clk_dev_data [] = {
226
+ static const struct imx95_blk_ctl_clk_dev_data imx95_dispmix_csr_clk_dev_data [] = {
227
227
[IMX95_CLK_DISPMIX_ENG0_SEL ] = {
228
228
.name = "disp_engine0_sel" ,
229
- .parent_names = disp_engine_parents ,
230
- .num_parents = ARRAY_SIZE (disp_engine_parents ),
229
+ .parent_names = imx95_disp_engine_parents ,
230
+ .num_parents = ARRAY_SIZE (imx95_disp_engine_parents ),
231
231
.reg = 0 ,
232
232
.bit_idx = 0 ,
233
233
.bit_width = 2 ,
@@ -236,8 +236,8 @@ static const struct imx95_blk_ctl_clk_dev_data dispmix_csr_clk_dev_data[] = {
236
236
},
237
237
[IMX95_CLK_DISPMIX_ENG1_SEL ] = {
238
238
.name = "disp_engine1_sel" ,
239
- .parent_names = disp_engine_parents ,
240
- .num_parents = ARRAY_SIZE (disp_engine_parents ),
239
+ .parent_names = imx95_disp_engine_parents ,
240
+ .num_parents = ARRAY_SIZE (imx95_disp_engine_parents ),
241
241
.reg = 0 ,
242
242
.bit_idx = 2 ,
243
243
.bit_width = 2 ,
@@ -246,9 +246,9 @@ static const struct imx95_blk_ctl_clk_dev_data dispmix_csr_clk_dev_data[] = {
246
246
}
247
247
};
248
248
249
- static const struct imx95_blk_ctl_dev_data dispmix_csr_dev_data = {
250
- .num_clks = ARRAY_SIZE (dispmix_csr_clk_dev_data ),
251
- .clk_dev_data = dispmix_csr_clk_dev_data ,
249
+ static const struct imx95_blk_ctl_dev_data imx95_dispmix_csr_dev_data = {
250
+ .num_clks = ARRAY_SIZE (imx95_dispmix_csr_clk_dev_data ),
251
+ .clk_dev_data = imx95_dispmix_csr_clk_dev_data ,
252
252
.clk_reg_offset = 0 ,
253
253
};
254
254
@@ -469,8 +469,8 @@ static const struct dev_pm_ops imx95_bc_pm_ops = {
469
469
static const struct of_device_id imx95_bc_of_match [] = {
470
470
{ .compatible = "nxp,imx95-camera-csr" , .data = & camblk_dev_data },
471
471
{ .compatible = "nxp,imx95-display-master-csr" , },
472
- { .compatible = "nxp,imx95-lvds -csr" , .data = & lvds_csr_dev_data },
473
- { .compatible = "nxp,imx95-display -csr" , .data = & dispmix_csr_dev_data },
472
+ { .compatible = "nxp,imx95-display -csr" , .data = & imx95_dispmix_csr_dev_data },
473
+ { .compatible = "nxp,imx95-lvds -csr" , .data = & imx95_lvds_csr_dev_data },
474
474
{ .compatible = "nxp,imx95-hsio-blk-ctl" , .data = & hsio_blk_ctl_dev_data },
475
475
{ .compatible = "nxp,imx95-vpu-csr" , .data = & vpublk_dev_data },
476
476
{ .compatible = "nxp,imx95-netcmix-blk-ctrl" , .data = & netcmix_dev_data },
0 commit comments