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prabhakarladgeertu
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clk: renesas: Add CPG/MSSR support to RZ/N2H SoC
Add clock driver support for the Renesas RZ/N2H (R9A09G087) SoC by reusing the existing RZ/T2H (R9A09G077) CPG/MSSR implementation, as both SoCs share the same clock and reset architecture. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
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drivers/clk/renesas/Kconfig

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@@ -44,6 +44,7 @@ config CLK_RENESAS
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select CLK_R9A09G056 if ARCH_R9A09G056
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select CLK_R9A09G057 if ARCH_R9A09G057
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select CLK_R9A09G077 if ARCH_R9A09G077
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select CLK_R9A09G087 if ARCH_R9A09G087
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select CLK_SH73A0 if ARCH_SH73A0
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if CLK_RENESAS
@@ -213,6 +214,10 @@ config CLK_R9A09G077
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bool "RZ/T2H clock support" if COMPILE_TEST
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select CLK_RENESAS_CPG_MSSR
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config CLK_R9A09G087
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bool "RZ/N2H clock support" if COMPILE_TEST
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select CLK_RENESAS_CPG_MSSR
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config CLK_SH73A0
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bool "SH-Mobile AG5 clock support" if COMPILE_TEST
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select CLK_RENESAS_CPG_MSTP

drivers/clk/renesas/Makefile

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@@ -41,6 +41,7 @@ obj-$(CONFIG_CLK_R9A09G047) += r9a09g047-cpg.o
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obj-$(CONFIG_CLK_R9A09G056) += r9a09g056-cpg.o
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obj-$(CONFIG_CLK_R9A09G057) += r9a09g057-cpg.o
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obj-$(CONFIG_CLK_R9A09G077) += r9a09g077-cpg.o
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obj-$(CONFIG_CLK_R9A09G087) += r9a09g077-cpg.o
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obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
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# Family

drivers/clk/renesas/r9a09g077-cpg.c

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@@ -13,6 +13,7 @@
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#include <linux/kernel.h>
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#include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
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#include <dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h>
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#include "renesas-cpg-mssr.h"
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#define RZT2H_REG_BLOCK_SHIFT 11

drivers/clk/renesas/renesas-cpg-mssr.c

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@@ -941,6 +941,12 @@ static const struct of_device_id cpg_mssr_match[] = {
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.compatible = "renesas,r9a09g077-cpg-mssr",
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.data = &r9a09g077_cpg_mssr_info,
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},
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#endif
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#ifdef CONFIG_CLK_R9A09G087
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{
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.compatible = "renesas,r9a09g087-cpg-mssr",
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.data = &r9a09g077_cpg_mssr_info,
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},
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#endif
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{ /* sentinel */ }
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};

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