Skip to content

Commit 92640a6

Browse files
stephan-ghandersson
authored andcommitted
clk: qcom: videocc-sm8550: Add separate frequency tables for X1E80100
X1E80100 videocc is identical to the one in SM8550, aside from slightly different recommended PLL frequencies. Add the separate frequency tables for that and apply them if the qcom,x1e80100-videocc compatible is used. Reviewed-by: Bryan O'Donoghue <[email protected]> Signed-off-by: Stephan Gerhold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
1 parent b7b0799 commit 92640a6

File tree

2 files changed

+30
-1
lines changed

2 files changed

+30
-1
lines changed

drivers/clk/qcom/Kconfig

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1429,7 +1429,7 @@ config SM_VIDEOCC_8550
14291429
select QCOM_GDSC
14301430
help
14311431
Support for the video clock controller on Qualcomm Technologies, Inc.
1432-
SM8550 or SM8650 devices.
1432+
SM8550 or SM8650 or X1E80100 devices.
14331433
Say Y if you want to support video devices and functionality such as
14341434
video encode/decode.
14351435

drivers/clk/qcom/videocc-sm8550.c

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -145,6 +145,16 @@ static const struct freq_tbl ftbl_video_cc_mvs0_clk_src_sm8650[] = {
145145
{ }
146146
};
147147

148+
static const struct freq_tbl ftbl_video_cc_mvs0_clk_src_x1e80100[] = {
149+
F(576000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
150+
F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
151+
F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
152+
F(1098000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
153+
F(1332000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
154+
F(1443000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
155+
{ }
156+
};
157+
148158
static struct clk_rcg2 video_cc_mvs0_clk_src = {
149159
.cmd_rcgr = 0x8000,
150160
.mnd_width = 0,
@@ -177,6 +187,15 @@ static const struct freq_tbl ftbl_video_cc_mvs1_clk_src_sm8650[] = {
177187
{ }
178188
};
179189

190+
static const struct freq_tbl ftbl_video_cc_mvs1_clk_src_x1e80100[] = {
191+
F(840000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
192+
F(1050000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
193+
F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
194+
F(1500000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
195+
F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
196+
{ }
197+
};
198+
180199
static struct clk_rcg2 video_cc_mvs1_clk_src = {
181200
.cmd_rcgr = 0x8018,
182201
.mnd_width = 0,
@@ -559,12 +578,22 @@ static const struct qcom_cc_desc video_cc_sm8550_desc = {
559578
static const struct of_device_id video_cc_sm8550_match_table[] = {
560579
{ .compatible = "qcom,sm8550-videocc" },
561580
{ .compatible = "qcom,sm8650-videocc" },
581+
{ .compatible = "qcom,x1e80100-videocc" },
562582
{ }
563583
};
564584
MODULE_DEVICE_TABLE(of, video_cc_sm8550_match_table);
565585

566586
static int video_cc_sm8550_probe(struct platform_device *pdev)
567587
{
588+
if (of_device_is_compatible(pdev->dev.of_node, "qcom,x1e80100-videocc")) {
589+
video_cc_pll0_config.l = 0x1e;
590+
video_cc_pll0_config.alpha = 0x0000;
591+
video_cc_pll1_config.l = 0x2b;
592+
video_cc_pll1_config.alpha = 0xc000;
593+
video_cc_mvs0_clk_src.freq_tbl = ftbl_video_cc_mvs0_clk_src_x1e80100;
594+
video_cc_mvs1_clk_src.freq_tbl = ftbl_video_cc_mvs1_clk_src_x1e80100;
595+
}
596+
568597
if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8650-videocc")) {
569598
video_cc_pll0_config.l = 0x1e;
570599
video_cc_pll0_config.alpha = 0xa000;

0 commit comments

Comments
 (0)