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Merge tag 'x86-platform-2025-07-29' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 platform updates from Ingo Molnar: "This adds support for the AMD hardware feedback interface (HFI), by Perry Yuan" * tag 'x86-platform-2025-07-29' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/itmt: Add debugfs file to show core priorities platform/x86/amd: hfi: Add debugfs support platform/x86/amd: hfi: Set ITMT priority from ranking data cpufreq/amd-pstate: Disable preferred cores on designs with workload classification x86/process: Clear hardware feedback history for AMD processors platform/x86: hfi: Add power management callback platform/x86: hfi: Add online and offline callback support platform/x86: hfi: Init per-cpu scores for each class platform/x86: hfi: Parse CPU core ranking data from shared memory platform/x86: hfi: Introduce AMD Hardware Feedback Interface Driver x86/msr-index: Add AMD workload classification MSRs MAINTAINERS: Add maintainer entry for AMD Hardware Feedback Driver Documentation/x86: Add AMD Hardware Feedback Interface documentation
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‎Documentation/arch/x86/amd-hfi.rst

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.. SPDX-License-Identifier: GPL-2.0
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======================================================================
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Hardware Feedback Interface For Hetero Core Scheduling On AMD Platform
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======================================================================
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:Copyright: 2025 Advanced Micro Devices, Inc. All Rights Reserved.
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:Author: Perry Yuan <[email protected]>
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:Author: Mario Limonciello <[email protected]>
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Overview
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--------
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AMD Heterogeneous Core implementations are comprised of more than one
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architectural class and CPUs are comprised of cores of various efficiency and
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power capabilities: performance-oriented *classic cores* and power-efficient
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*dense cores*. As such, power management strategies must be designed to
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accommodate the complexities introduced by incorporating different core types.
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Heterogeneous systems can also extend to more than two architectural classes
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as well. The purpose of the scheduling feedback mechanism is to provide
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information to the operating system scheduler in real time such that the
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scheduler can direct threads to the optimal core.
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The goal of AMD's heterogeneous architecture is to attain power benefit by
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sending background threads to the dense cores while sending high priority
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threads to the classic cores. From a performance perspective, sending
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background threads to dense cores can free up power headroom and allow the
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classic cores to optimally service demanding threads. Furthermore, the area
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optimized nature of the dense cores allows for an increasing number of
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physical cores. This improved core density will have positive multithreaded
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performance impact.
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AMD Heterogeneous Core Driver
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-----------------------------
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The ``amd_hfi`` driver delivers the operating system a performance and energy
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efficiency capability data for each CPU in the system. The scheduler can use
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the ranking data from the HFI driver to make task placement decisions.
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Thread Classification and Ranking Table Interaction
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----------------------------------------------------
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The thread classification is used to select into a ranking table that
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describes an efficiency and performance ranking for each classification.
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Threads are classified during runtime into enumerated classes. The classes
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represent thread performance/power characteristics that may benefit from
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special scheduling behaviors. The below table depicts an example of thread
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classification and a preference where a given thread should be scheduled
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based on its thread class. The real time thread classification is consumed
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by the operating system and is used to inform the scheduler of where the
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thread should be placed.
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Thread Classification Example Table
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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+----------+----------------+-------------------------------+---------------------+---------+
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| class ID | Classification | Preferred scheduling behavior | Preemption priority | Counter |
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+----------+----------------+-------------------------------+---------------------+---------+
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| 0 | Default | Performant | Highest | |
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+----------+----------------+-------------------------------+---------------------+---------+
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| 1 | Non-scalable | Efficient | Lowest | PMCx1A1 |
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+----------+----------------+-------------------------------+---------------------+---------+
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| 2 | I/O bound | Efficient | Lowest | PMCx044 |
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+----------+----------------+-------------------------------+---------------------+---------+
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Thread classification is performed by the hardware each time that the thread is switched out.
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Threads that don't meet any hardware specified criteria are classified as "default".
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AMD Hardware Feedback Interface
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--------------------------------
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The Hardware Feedback Interface provides to the operating system information
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about the performance and energy efficiency of each CPU in the system. Each
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capability is given as a unit-less quantity in the range [0-255]. A higher
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performance value indicates higher performance capability, and a higher
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efficiency value indicates more efficiency. Energy efficiency and performance
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are reported in separate capabilities in the shared memory based ranking table.
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These capabilities may change at runtime as a result of changes in the
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operating conditions of the system or the action of external factors.
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Power Management firmware is responsible for detecting events that require
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a reordering of the performance and efficiency ranking. Table updates happen
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relatively infrequently and occur on the time scale of seconds or more.
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The following events trigger a table update:
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* Thermal Stress Events
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* Silent Compute
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* Extreme Low Battery Scenarios
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The kernel or a userspace policy daemon can use these capabilities to modify
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task placement decisions. For instance, if either the performance or energy
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capabilities of a given logical processor becomes zero, it is an indication
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that the hardware recommends to the operating system to not schedule any tasks
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on that processor for performance or energy efficiency reasons, respectively.
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Implementation details for Linux
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--------------------------------
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The implementation of threads scheduling consists of the following steps:
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1. A thread is spawned and scheduled to the ideal core using the default
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heterogeneous scheduling policy.
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2. The processor profiles thread execution and assigns an enumerated
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classification ID.
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This classification is communicated to the OS via logical processor
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scope MSR.
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3. During the thread context switch out the operating system consumes the
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workload (WL) classification which resides in a logical processor scope MSR.
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4. The OS triggers the hardware to clear its history by writing to an MSR,
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after consuming the WL classification and before switching in the new thread.
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5. If due to the classification, ranking table, and processor availability,
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the thread is not on its ideal processor, the OS will then consider
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scheduling the thread on its ideal processor (if available).
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Ranking Table
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-------------
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The ranking table is a shared memory region that is used to communicate the
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performance and energy efficiency capabilities of each CPU in the system.
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The ranking table design includes rankings for each APIC ID in the system and
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rankings both for performance and efficiency for each workload classification.
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.. kernel-doc:: drivers/platform/x86/amd/hfi/hfi.c
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:doc: amd_shmem_info
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Ranking Table update
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---------------------------
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The power management firmware issues an platform interrupt after updating the
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ranking table and is ready for the operating system to consume it. CPUs receive
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such interrupt and read new ranking table from shared memory which PCCT table
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has provided, then ``amd_hfi`` driver parses the new table to provide new
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consume data for scheduling decisions.

‎Documentation/arch/x86/index.rst

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amd-debugging
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amd-memory-encryption
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amd_hsmp
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amd-hfi
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tdx
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pti
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mds

‎MAINTAINERS

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F: arch/x86/include/uapi/asm/amd_hsmp.h
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F: drivers/platform/x86/amd/hsmp/
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AMD HETERO CORE HARDWARE FEEDBACK DRIVER
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M: Mario Limonciello <[email protected]>
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R: Perry Yuan <[email protected]>
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L: [email protected]
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S: Supported
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B: https://gitlab.freedesktop.org/drm/amd/-/issues
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F: Documentation/arch/x86/amd-hfi.rst
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F: drivers/platform/x86/amd/hfi/
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AMD IOMMU (AMD-VI)
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M: Joerg Roedel <[email protected]>
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R: Suravee Suthikulpanit <[email protected]>

‎arch/x86/include/asm/msr-index.h

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#define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301
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#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302
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/* AMD Hardware Feedback Support MSRs */
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#define MSR_AMD_WORKLOAD_CLASS_CONFIG 0xc0000500
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#define MSR_AMD_WORKLOAD_CLASS_ID 0xc0000501
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#define MSR_AMD_WORKLOAD_HRST 0xc0000502
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/* AMD Last Branch Record MSRs */
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#define MSR_AMD64_LBR_SELECT 0xc000010e
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‎arch/x86/kernel/itmt.c

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return result;
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}
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static int sched_core_priority_show(struct seq_file *s, void *unused)
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{
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int cpu;
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seq_puts(s, "CPU #\tPriority\n");
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for_each_possible_cpu(cpu)
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seq_printf(s, "%d\t%d\n", cpu, arch_asym_cpu_priority(cpu));
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return 0;
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}
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DEFINE_SHOW_ATTRIBUTE(sched_core_priority);
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static const struct file_operations dfs_sched_itmt_fops = {
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.read = debugfs_read_file_bool,
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.write = sched_itmt_enabled_write,
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};
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static struct dentry *dfs_sched_itmt;
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static struct dentry *dfs_sched_core_prio;
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/**
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* sched_set_itmt_support() - Indicate platform supports ITMT
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return -ENOMEM;
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}
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dfs_sched_core_prio = debugfs_create_file("sched_core_priority", 0644,
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arch_debugfs_dir, NULL,
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&sched_core_priority_fops);
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if (IS_ERR_OR_NULL(dfs_sched_core_prio)) {
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dfs_sched_core_prio = NULL;
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return -ENOMEM;
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}
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sched_itmt_capable = true;
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sysctl_sched_itmt_enabled = 1;
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debugfs_remove(dfs_sched_itmt);
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dfs_sched_itmt = NULL;
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debugfs_remove(dfs_sched_core_prio);
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dfs_sched_core_prio = NULL;
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if (sysctl_sched_itmt_enabled) {
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/* disable sched_itmt if we are no longer ITMT capable */

‎arch/x86/kernel/process_64.c

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/* Load the Intel cache allocation PQR MSR. */
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resctrl_arch_sched_in(next_p);
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/* Reset hw history on AMD CPUs */
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if (cpu_feature_enabled(X86_FEATURE_AMD_WORKLOAD_CLASS))
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wrmsrl(MSR_AMD_WORKLOAD_HRST, 0x1);
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return prev_p;
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}
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‎drivers/cpufreq/amd-pstate.c

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if (!amd_pstate_prefcore)
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return;
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/* should use amd-hfi instead */
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if (cpu_feature_enabled(X86_FEATURE_AMD_WORKLOAD_CLASS) &&
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IS_ENABLED(CONFIG_AMD_HFI)) {
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amd_pstate_prefcore = false;
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return;
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}
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cpudata->hw_prefcore = true;
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/* Priorities must be initialized before ITMT support can be toggled on. */

‎drivers/platform/x86/amd/Kconfig

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source "drivers/platform/x86/amd/hsmp/Kconfig"
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source "drivers/platform/x86/amd/pmf/Kconfig"
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source "drivers/platform/x86/amd/pmc/Kconfig"
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source "drivers/platform/x86/amd/hfi/Kconfig"
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config AMD_3D_VCACHE
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tristate "AMD 3D V-Cache Performance Optimizer Driver"

‎drivers/platform/x86/amd/Makefile

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obj-$(CONFIG_AMD_PMF) += pmf/
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obj-$(CONFIG_AMD_WBRF) += wbrf.o
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obj-$(CONFIG_AMD_ISP_PLATFORM) += amd_isp4.o
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obj-$(CONFIG_AMD_HFI) += hfi/

‎drivers/platform/x86/amd/hfi/Kconfig

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# SPDX-License-Identifier: GPL-2.0-only
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#
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# AMD Hardware Feedback Interface Driver
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#
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config AMD_HFI
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bool "AMD Hetero Core Hardware Feedback Driver"
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depends on ACPI
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depends on CPU_SUP_AMD
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depends on SCHED_MC_PRIO
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help
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Select this option to enable the AMD Heterogeneous Core Hardware
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Feedback Interface. If selected, hardware provides runtime thread
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classification guidance to the operating system on the performance and
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energy efficiency capabilities of each heterogeneous CPU core. These
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capabilities may vary due to the inherent differences in the core types
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and can also change as a result of variations in the operating
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conditions of the system such as power and thermal limits.

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