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alexelderdlan17
alexelder
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soc: spacemit: create a header for clock/reset registers
Move the definitions of register offsets and fields used by the SpacemiT K1 SoC CCUs into a separate header file, so that they can be shared by the reset driver that will be found under drivers/reset. Signed-off-by: Alex Elder <[email protected]> Reviewed-by: Haylen Chu <[email protected]> Reviewed-by: Yixun Lan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Yixun Lan <[email protected]>
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‎drivers/clk/spacemit/ccu-k1.c

Lines changed: 1 addition & 110 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@
1111
#include <linux/minmax.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
14+
#include <soc/spacemit/k1-syscon.h>
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1516
#include "ccu_common.h"
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#include "ccu_pll.h"
@@ -19,116 +20,6 @@
1920

2021
#include <dt-bindings/clock/spacemit,k1-syscon.h>
2122

22-
/* APBS register offset */
23-
#define APBS_PLL1_SWCR1 0x100
24-
#define APBS_PLL1_SWCR2 0x104
25-
#define APBS_PLL1_SWCR3 0x108
26-
#define APBS_PLL2_SWCR1 0x118
27-
#define APBS_PLL2_SWCR2 0x11c
28-
#define APBS_PLL2_SWCR3 0x120
29-
#define APBS_PLL3_SWCR1 0x124
30-
#define APBS_PLL3_SWCR2 0x128
31-
#define APBS_PLL3_SWCR3 0x12c
32-
33-
/* MPMU register offset */
34-
#define MPMU_POSR 0x0010
35-
#define POSR_PLL1_LOCK BIT(27)
36-
#define POSR_PLL2_LOCK BIT(28)
37-
#define POSR_PLL3_LOCK BIT(29)
38-
#define MPMU_SUCCR 0x0014
39-
#define MPMU_ISCCR 0x0044
40-
#define MPMU_WDTPCR 0x0200
41-
#define MPMU_RIPCCR 0x0210
42-
#define MPMU_ACGR 0x1024
43-
#define MPMU_APBCSCR 0x1050
44-
#define MPMU_SUCCR_1 0x10b0
45-
46-
/* APBC register offset */
47-
#define APBC_UART1_CLK_RST 0x00
48-
#define APBC_UART2_CLK_RST 0x04
49-
#define APBC_GPIO_CLK_RST 0x08
50-
#define APBC_PWM0_CLK_RST 0x0c
51-
#define APBC_PWM1_CLK_RST 0x10
52-
#define APBC_PWM2_CLK_RST 0x14
53-
#define APBC_PWM3_CLK_RST 0x18
54-
#define APBC_TWSI8_CLK_RST 0x20
55-
#define APBC_UART3_CLK_RST 0x24
56-
#define APBC_RTC_CLK_RST 0x28
57-
#define APBC_TWSI0_CLK_RST 0x2c
58-
#define APBC_TWSI1_CLK_RST 0x30
59-
#define APBC_TIMERS1_CLK_RST 0x34
60-
#define APBC_TWSI2_CLK_RST 0x38
61-
#define APBC_AIB_CLK_RST 0x3c
62-
#define APBC_TWSI4_CLK_RST 0x40
63-
#define APBC_TIMERS2_CLK_RST 0x44
64-
#define APBC_ONEWIRE_CLK_RST 0x48
65-
#define APBC_TWSI5_CLK_RST 0x4c
66-
#define APBC_DRO_CLK_RST 0x58
67-
#define APBC_IR_CLK_RST 0x5c
68-
#define APBC_TWSI6_CLK_RST 0x60
69-
#define APBC_COUNTER_CLK_SEL 0x64
70-
#define APBC_TWSI7_CLK_RST 0x68
71-
#define APBC_TSEN_CLK_RST 0x6c
72-
#define APBC_UART4_CLK_RST 0x70
73-
#define APBC_UART5_CLK_RST 0x74
74-
#define APBC_UART6_CLK_RST 0x78
75-
#define APBC_SSP3_CLK_RST 0x7c
76-
#define APBC_SSPA0_CLK_RST 0x80
77-
#define APBC_SSPA1_CLK_RST 0x84
78-
#define APBC_IPC_AP2AUD_CLK_RST 0x90
79-
#define APBC_UART7_CLK_RST 0x94
80-
#define APBC_UART8_CLK_RST 0x98
81-
#define APBC_UART9_CLK_RST 0x9c
82-
#define APBC_CAN0_CLK_RST 0xa0
83-
#define APBC_PWM4_CLK_RST 0xa8
84-
#define APBC_PWM5_CLK_RST 0xac
85-
#define APBC_PWM6_CLK_RST 0xb0
86-
#define APBC_PWM7_CLK_RST 0xb4
87-
#define APBC_PWM8_CLK_RST 0xb8
88-
#define APBC_PWM9_CLK_RST 0xbc
89-
#define APBC_PWM10_CLK_RST 0xc0
90-
#define APBC_PWM11_CLK_RST 0xc4
91-
#define APBC_PWM12_CLK_RST 0xc8
92-
#define APBC_PWM13_CLK_RST 0xcc
93-
#define APBC_PWM14_CLK_RST 0xd0
94-
#define APBC_PWM15_CLK_RST 0xd4
95-
#define APBC_PWM16_CLK_RST 0xd8
96-
#define APBC_PWM17_CLK_RST 0xdc
97-
#define APBC_PWM18_CLK_RST 0xe0
98-
#define APBC_PWM19_CLK_RST 0xe4
99-
100-
/* APMU register offset */
101-
#define APMU_JPG_CLK_RES_CTRL 0x020
102-
#define APMU_CSI_CCIC2_CLK_RES_CTRL 0x024
103-
#define APMU_ISP_CLK_RES_CTRL 0x038
104-
#define APMU_LCD_CLK_RES_CTRL1 0x044
105-
#define APMU_LCD_SPI_CLK_RES_CTRL 0x048
106-
#define APMU_LCD_CLK_RES_CTRL2 0x04c
107-
#define APMU_CCIC_CLK_RES_CTRL 0x050
108-
#define APMU_SDH0_CLK_RES_CTRL 0x054
109-
#define APMU_SDH1_CLK_RES_CTRL 0x058
110-
#define APMU_USB_CLK_RES_CTRL 0x05c
111-
#define APMU_QSPI_CLK_RES_CTRL 0x060
112-
#define APMU_DMA_CLK_RES_CTRL 0x064
113-
#define APMU_AES_CLK_RES_CTRL 0x068
114-
#define APMU_VPU_CLK_RES_CTRL 0x0a4
115-
#define APMU_GPU_CLK_RES_CTRL 0x0cc
116-
#define APMU_SDH2_CLK_RES_CTRL 0x0e0
117-
#define APMU_PMUA_MC_CTRL 0x0e8
118-
#define APMU_PMU_CC2_AP 0x100
119-
#define APMU_PMUA_EM_CLK_RES_CTRL 0x104
120-
#define APMU_AUDIO_CLK_RES_CTRL 0x14c
121-
#define APMU_HDMI_CLK_RES_CTRL 0x1b8
122-
#define APMU_CCI550_CLK_CTRL 0x300
123-
#define APMU_ACLK_CLK_CTRL 0x388
124-
#define APMU_CPU_C0_CLK_CTRL 0x38C
125-
#define APMU_CPU_C1_CLK_CTRL 0x390
126-
#define APMU_PCIE_CLK_RES_CTRL_0 0x3cc
127-
#define APMU_PCIE_CLK_RES_CTRL_1 0x3d4
128-
#define APMU_PCIE_CLK_RES_CTRL_2 0x3dc
129-
#define APMU_EMAC0_CLK_RES_CTRL 0x3e4
130-
#define APMU_EMAC1_CLK_RES_CTRL 0x3ec
131-
13223
struct spacemit_ccu_data {
13324
struct clk_hw **hws;
13425
size_t num;

‎include/soc/spacemit/k1-syscon.h

Lines changed: 118 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,118 @@
1+
/* SPDX-License-Identifier: GPL-2.0-only */
2+
3+
/* SpacemiT clock and reset driver definitions for the K1 SoC */
4+
5+
#ifndef __SOC_K1_SYSCON_H__
6+
#define __SOC_K1_SYSCON_H__
7+
8+
/* APBS register offset */
9+
#define APBS_PLL1_SWCR1 0x100
10+
#define APBS_PLL1_SWCR2 0x104
11+
#define APBS_PLL1_SWCR3 0x108
12+
#define APBS_PLL2_SWCR1 0x118
13+
#define APBS_PLL2_SWCR2 0x11c
14+
#define APBS_PLL2_SWCR3 0x120
15+
#define APBS_PLL3_SWCR1 0x124
16+
#define APBS_PLL3_SWCR2 0x128
17+
#define APBS_PLL3_SWCR3 0x12c
18+
19+
/* MPMU register offset */
20+
#define MPMU_POSR 0x0010
21+
#define POSR_PLL1_LOCK BIT(27)
22+
#define POSR_PLL2_LOCK BIT(28)
23+
#define POSR_PLL3_LOCK BIT(29)
24+
#define MPMU_SUCCR 0x0014
25+
#define MPMU_ISCCR 0x0044
26+
#define MPMU_WDTPCR 0x0200
27+
#define MPMU_RIPCCR 0x0210
28+
#define MPMU_ACGR 0x1024
29+
#define MPMU_APBCSCR 0x1050
30+
#define MPMU_SUCCR_1 0x10b0
31+
32+
/* APBC register offset */
33+
#define APBC_UART1_CLK_RST 0x00
34+
#define APBC_UART2_CLK_RST 0x04
35+
#define APBC_GPIO_CLK_RST 0x08
36+
#define APBC_PWM0_CLK_RST 0x0c
37+
#define APBC_PWM1_CLK_RST 0x10
38+
#define APBC_PWM2_CLK_RST 0x14
39+
#define APBC_PWM3_CLK_RST 0x18
40+
#define APBC_TWSI8_CLK_RST 0x20
41+
#define APBC_UART3_CLK_RST 0x24
42+
#define APBC_RTC_CLK_RST 0x28
43+
#define APBC_TWSI0_CLK_RST 0x2c
44+
#define APBC_TWSI1_CLK_RST 0x30
45+
#define APBC_TIMERS1_CLK_RST 0x34
46+
#define APBC_TWSI2_CLK_RST 0x38
47+
#define APBC_AIB_CLK_RST 0x3c
48+
#define APBC_TWSI4_CLK_RST 0x40
49+
#define APBC_TIMERS2_CLK_RST 0x44
50+
#define APBC_ONEWIRE_CLK_RST 0x48
51+
#define APBC_TWSI5_CLK_RST 0x4c
52+
#define APBC_DRO_CLK_RST 0x58
53+
#define APBC_IR_CLK_RST 0x5c
54+
#define APBC_TWSI6_CLK_RST 0x60
55+
#define APBC_COUNTER_CLK_SEL 0x64
56+
#define APBC_TWSI7_CLK_RST 0x68
57+
#define APBC_TSEN_CLK_RST 0x6c
58+
#define APBC_UART4_CLK_RST 0x70
59+
#define APBC_UART5_CLK_RST 0x74
60+
#define APBC_UART6_CLK_RST 0x78
61+
#define APBC_SSP3_CLK_RST 0x7c
62+
#define APBC_SSPA0_CLK_RST 0x80
63+
#define APBC_SSPA1_CLK_RST 0x84
64+
#define APBC_IPC_AP2AUD_CLK_RST 0x90
65+
#define APBC_UART7_CLK_RST 0x94
66+
#define APBC_UART8_CLK_RST 0x98
67+
#define APBC_UART9_CLK_RST 0x9c
68+
#define APBC_CAN0_CLK_RST 0xa0
69+
#define APBC_PWM4_CLK_RST 0xa8
70+
#define APBC_PWM5_CLK_RST 0xac
71+
#define APBC_PWM6_CLK_RST 0xb0
72+
#define APBC_PWM7_CLK_RST 0xb4
73+
#define APBC_PWM8_CLK_RST 0xb8
74+
#define APBC_PWM9_CLK_RST 0xbc
75+
#define APBC_PWM10_CLK_RST 0xc0
76+
#define APBC_PWM11_CLK_RST 0xc4
77+
#define APBC_PWM12_CLK_RST 0xc8
78+
#define APBC_PWM13_CLK_RST 0xcc
79+
#define APBC_PWM14_CLK_RST 0xd0
80+
#define APBC_PWM15_CLK_RST 0xd4
81+
#define APBC_PWM16_CLK_RST 0xd8
82+
#define APBC_PWM17_CLK_RST 0xdc
83+
#define APBC_PWM18_CLK_RST 0xe0
84+
#define APBC_PWM19_CLK_RST 0xe4
85+
86+
/* APMU register offset */
87+
#define APMU_JPG_CLK_RES_CTRL 0x020
88+
#define APMU_CSI_CCIC2_CLK_RES_CTRL 0x024
89+
#define APMU_ISP_CLK_RES_CTRL 0x038
90+
#define APMU_LCD_CLK_RES_CTRL1 0x044
91+
#define APMU_LCD_SPI_CLK_RES_CTRL 0x048
92+
#define APMU_LCD_CLK_RES_CTRL2 0x04c
93+
#define APMU_CCIC_CLK_RES_CTRL 0x050
94+
#define APMU_SDH0_CLK_RES_CTRL 0x054
95+
#define APMU_SDH1_CLK_RES_CTRL 0x058
96+
#define APMU_USB_CLK_RES_CTRL 0x05c
97+
#define APMU_QSPI_CLK_RES_CTRL 0x060
98+
#define APMU_DMA_CLK_RES_CTRL 0x064
99+
#define APMU_AES_CLK_RES_CTRL 0x068
100+
#define APMU_VPU_CLK_RES_CTRL 0x0a4
101+
#define APMU_GPU_CLK_RES_CTRL 0x0cc
102+
#define APMU_SDH2_CLK_RES_CTRL 0x0e0
103+
#define APMU_PMUA_MC_CTRL 0x0e8
104+
#define APMU_PMU_CC2_AP 0x100
105+
#define APMU_PMUA_EM_CLK_RES_CTRL 0x104
106+
#define APMU_AUDIO_CLK_RES_CTRL 0x14c
107+
#define APMU_HDMI_CLK_RES_CTRL 0x1b8
108+
#define APMU_CCI550_CLK_CTRL 0x300
109+
#define APMU_ACLK_CLK_CTRL 0x388
110+
#define APMU_CPU_C0_CLK_CTRL 0x38C
111+
#define APMU_CPU_C1_CLK_CTRL 0x390
112+
#define APMU_PCIE_CLK_RES_CTRL_0 0x3cc
113+
#define APMU_PCIE_CLK_RES_CTRL_1 0x3d4
114+
#define APMU_PCIE_CLK_RES_CTRL_2 0x3dc
115+
#define APMU_EMAC0_CLK_RES_CTRL 0x3e4
116+
#define APMU_EMAC1_CLK_RES_CTRL 0x3ec
117+
118+
#endif /* __SOC_K1_SYSCON_H__ */

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