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alexelderdlan17
alexelder
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reset: spacemit: add support for SpacemiT CCU resets
Implement reset support for SpacemiT CCUs. A SpacemiT reset controller device is an auxiliary device associated with a clock controller (CCU). This patch defines the reset controllers for the MPMU, APBC, and MPMU CCUs, which already define clock controllers. It also adds RCPU, RCPU2, and ACPB2 CCUs, which only define resets. Signed-off-by: Alex Elder <[email protected]> Reviewed-by: Philipp Zabel <[email protected]> Reviewed-by: Yixun Lan <[email protected]> Acked-by: Philipp Zabel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Yixun Lan <[email protected]>
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‎drivers/reset/Kconfig

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@@ -270,6 +270,15 @@ config RESET_SOCFPGA
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This enables the reset driver for the SoCFPGA ARMv7 platforms. This
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driver gets initialized early during platform init calls.
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config RESET_SPACEMIT
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tristate "SpacemiT reset driver"
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depends on ARCH_SPACEMIT || COMPILE_TEST
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select AUXILIARY_BUS
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default ARCH_SPACEMIT
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help
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This enables the reset controller driver for SpacemiT SoCs,
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including the K1.
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config RESET_SUNPLUS
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bool "Sunplus SoCs Reset Driver" if COMPILE_TEST
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default ARCH_SUNPLUS

‎drivers/reset/Makefile

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@@ -35,6 +35,7 @@ obj-$(CONFIG_RESET_RZV2H_USB2PHY) += reset-rzv2h-usb2phy.o
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obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
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obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
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obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
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obj-$(CONFIG_RESET_SPACEMIT) += reset-spacemit.o
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obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o
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obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
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obj-$(CONFIG_RESET_TH1520) += reset-th1520.o

‎drivers/reset/reset-spacemit.c

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@@ -0,0 +1,304 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/* SpacemiT reset controller driver */
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#include <linux/auxiliary_bus.h>
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#include <linux/container_of.h>
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/regmap.h>
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#include <linux/reset-controller.h>
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#include <linux/types.h>
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#include <soc/spacemit/k1-syscon.h>
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#include <dt-bindings/clock/spacemit,k1-syscon.h>
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struct ccu_reset_data {
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u32 offset;
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u32 assert_mask;
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u32 deassert_mask;
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};
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struct ccu_reset_controller_data {
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const struct ccu_reset_data *reset_data; /* array */
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size_t count;
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};
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struct ccu_reset_controller {
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struct reset_controller_dev rcdev;
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const struct ccu_reset_controller_data *data;
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struct regmap *regmap;
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};
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#define RESET_DATA(_offset, _assert_mask, _deassert_mask) \
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{ \
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.offset = (_offset), \
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.assert_mask = (_assert_mask), \
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.deassert_mask = (_deassert_mask), \
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}
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static const struct ccu_reset_data k1_mpmu_resets[] = {
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[RESET_WDT] = RESET_DATA(MPMU_WDTPCR, BIT(2), 0),
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};
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static const struct ccu_reset_controller_data k1_mpmu_reset_data = {
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.reset_data = k1_mpmu_resets,
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.count = ARRAY_SIZE(k1_mpmu_resets),
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};
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static const struct ccu_reset_data k1_apbc_resets[] = {
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[RESET_UART0] = RESET_DATA(APBC_UART1_CLK_RST, BIT(2), 0),
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[RESET_UART2] = RESET_DATA(APBC_UART2_CLK_RST, BIT(2), 0),
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[RESET_GPIO] = RESET_DATA(APBC_GPIO_CLK_RST, BIT(2), 0),
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[RESET_PWM0] = RESET_DATA(APBC_PWM0_CLK_RST, BIT(2), BIT(0)),
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[RESET_PWM1] = RESET_DATA(APBC_PWM1_CLK_RST, BIT(2), BIT(0)),
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[RESET_PWM2] = RESET_DATA(APBC_PWM2_CLK_RST, BIT(2), BIT(0)),
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[RESET_PWM3] = RESET_DATA(APBC_PWM3_CLK_RST, BIT(2), BIT(0)),
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[RESET_PWM4] = RESET_DATA(APBC_PWM4_CLK_RST, BIT(2), BIT(0)),
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[RESET_PWM5] = RESET_DATA(APBC_PWM5_CLK_RST, BIT(2), BIT(0)),
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[RESET_PWM6] = RESET_DATA(APBC_PWM6_CLK_RST, BIT(2), BIT(0)),
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[RESET_PWM7] = RESET_DATA(APBC_PWM7_CLK_RST, BIT(2), BIT(0)),
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[RESET_PWM8] = RESET_DATA(APBC_PWM8_CLK_RST, BIT(2), BIT(0)),
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[RESET_PWM9] = RESET_DATA(APBC_PWM9_CLK_RST, BIT(2), BIT(0)),
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[RESET_PWM10] = RESET_DATA(APBC_PWM10_CLK_RST, BIT(2), BIT(0)),
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[RESET_PWM11] = RESET_DATA(APBC_PWM11_CLK_RST, BIT(2), BIT(0)),
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[RESET_PWM12] = RESET_DATA(APBC_PWM12_CLK_RST, BIT(2), BIT(0)),
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[RESET_PWM13] = RESET_DATA(APBC_PWM13_CLK_RST, BIT(2), BIT(0)),
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[RESET_PWM14] = RESET_DATA(APBC_PWM14_CLK_RST, BIT(2), BIT(0)),
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[RESET_PWM15] = RESET_DATA(APBC_PWM15_CLK_RST, BIT(2), BIT(0)),
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[RESET_PWM16] = RESET_DATA(APBC_PWM16_CLK_RST, BIT(2), BIT(0)),
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[RESET_PWM17] = RESET_DATA(APBC_PWM17_CLK_RST, BIT(2), BIT(0)),
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[RESET_PWM18] = RESET_DATA(APBC_PWM18_CLK_RST, BIT(2), BIT(0)),
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[RESET_PWM19] = RESET_DATA(APBC_PWM19_CLK_RST, BIT(2), BIT(0)),
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[RESET_SSP3] = RESET_DATA(APBC_SSP3_CLK_RST, BIT(2), 0),
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[RESET_UART3] = RESET_DATA(APBC_UART3_CLK_RST, BIT(2), 0),
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[RESET_RTC] = RESET_DATA(APBC_RTC_CLK_RST, BIT(2), 0),
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[RESET_TWSI0] = RESET_DATA(APBC_TWSI0_CLK_RST, BIT(2), 0),
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[RESET_TIMERS1] = RESET_DATA(APBC_TIMERS1_CLK_RST, BIT(2), 0),
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[RESET_AIB] = RESET_DATA(APBC_AIB_CLK_RST, BIT(2), 0),
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[RESET_TIMERS2] = RESET_DATA(APBC_TIMERS2_CLK_RST, BIT(2), 0),
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[RESET_ONEWIRE] = RESET_DATA(APBC_ONEWIRE_CLK_RST, BIT(2), 0),
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[RESET_SSPA0] = RESET_DATA(APBC_SSPA0_CLK_RST, BIT(2), 0),
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[RESET_SSPA1] = RESET_DATA(APBC_SSPA1_CLK_RST, BIT(2), 0),
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[RESET_DRO] = RESET_DATA(APBC_DRO_CLK_RST, BIT(2), 0),
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[RESET_IR] = RESET_DATA(APBC_IR_CLK_RST, BIT(2), 0),
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[RESET_TWSI1] = RESET_DATA(APBC_TWSI1_CLK_RST, BIT(2), 0),
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[RESET_TSEN] = RESET_DATA(APBC_TSEN_CLK_RST, BIT(2), 0),
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[RESET_TWSI2] = RESET_DATA(APBC_TWSI2_CLK_RST, BIT(2), 0),
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[RESET_TWSI4] = RESET_DATA(APBC_TWSI4_CLK_RST, BIT(2), 0),
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[RESET_TWSI5] = RESET_DATA(APBC_TWSI5_CLK_RST, BIT(2), 0),
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[RESET_TWSI6] = RESET_DATA(APBC_TWSI6_CLK_RST, BIT(2), 0),
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[RESET_TWSI7] = RESET_DATA(APBC_TWSI7_CLK_RST, BIT(2), 0),
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[RESET_TWSI8] = RESET_DATA(APBC_TWSI8_CLK_RST, BIT(2), 0),
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[RESET_IPC_AP2AUD] = RESET_DATA(APBC_IPC_AP2AUD_CLK_RST, BIT(2), 0),
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[RESET_UART4] = RESET_DATA(APBC_UART4_CLK_RST, BIT(2), 0),
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[RESET_UART5] = RESET_DATA(APBC_UART5_CLK_RST, BIT(2), 0),
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[RESET_UART6] = RESET_DATA(APBC_UART6_CLK_RST, BIT(2), 0),
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[RESET_UART7] = RESET_DATA(APBC_UART7_CLK_RST, BIT(2), 0),
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[RESET_UART8] = RESET_DATA(APBC_UART8_CLK_RST, BIT(2), 0),
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[RESET_UART9] = RESET_DATA(APBC_UART9_CLK_RST, BIT(2), 0),
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[RESET_CAN0] = RESET_DATA(APBC_CAN0_CLK_RST, BIT(2), 0),
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};
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static const struct ccu_reset_controller_data k1_apbc_reset_data = {
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.reset_data = k1_apbc_resets,
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.count = ARRAY_SIZE(k1_apbc_resets),
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};
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static const struct ccu_reset_data k1_apmu_resets[] = {
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[RESET_CCIC_4X] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(1)),
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[RESET_CCIC1_PHY] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(2)),
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[RESET_SDH_AXI] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(0)),
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[RESET_SDH0] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)),
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[RESET_SDH1] = RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)),
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[RESET_SDH2] = RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)),
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[RESET_USBP1_AXI] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(4)),
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[RESET_USB_AXI] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(0)),
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[RESET_USB30_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(9)),
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[RESET_USB30_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(10)),
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[RESET_USB30_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(11)),
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[RESET_QSPI] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(1)),
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[RESET_QSPI_BUS] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(0)),
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[RESET_DMA] = RESET_DATA(APMU_DMA_CLK_RES_CTRL, 0, BIT(0)),
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[RESET_AES] = RESET_DATA(APMU_AES_CLK_RES_CTRL, 0, BIT(4)),
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[RESET_VPU] = RESET_DATA(APMU_VPU_CLK_RES_CTRL, 0, BIT(0)),
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[RESET_GPU] = RESET_DATA(APMU_GPU_CLK_RES_CTRL, 0, BIT(1)),
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[RESET_EMMC] = RESET_DATA(APMU_PMUA_EM_CLK_RES_CTRL, 0, BIT(1)),
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[RESET_EMMC_X] = RESET_DATA(APMU_PMUA_EM_CLK_RES_CTRL, 0, BIT(0)),
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[RESET_AUDIO_SYS] = RESET_DATA(APMU_AUDIO_CLK_RES_CTRL, 0, BIT(0)),
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[RESET_AUDIO_MCU] = RESET_DATA(APMU_AUDIO_CLK_RES_CTRL, 0, BIT(2)),
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[RESET_AUDIO_APMU] = RESET_DATA(APMU_AUDIO_CLK_RES_CTRL, 0, BIT(3)),
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[RESET_HDMI] = RESET_DATA(APMU_HDMI_CLK_RES_CTRL, 0, BIT(9)),
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[RESET_PCIE0_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_0, 0, BIT(3)),
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[RESET_PCIE0_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_0, 0, BIT(4)),
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[RESET_PCIE0_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_0, 0, BIT(5)),
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[RESET_PCIE0_GLOBAL] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_0, BIT(8), 0),
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[RESET_PCIE1_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_1, 0, BIT(3)),
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[RESET_PCIE1_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_1, 0, BIT(4)),
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[RESET_PCIE1_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_1, 0, BIT(5)),
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[RESET_PCIE1_GLOBAL] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_1, BIT(8), 0),
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[RESET_PCIE2_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_2, 0, BIT(3)),
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[RESET_PCIE2_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_2, 0, BIT(4)),
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[RESET_PCIE2_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_2, 0, BIT(5)),
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[RESET_PCIE2_GLOBAL] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_2, BIT(8), 0),
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[RESET_EMAC0] = RESET_DATA(APMU_EMAC0_CLK_RES_CTRL, 0, BIT(1)),
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[RESET_EMAC1] = RESET_DATA(APMU_EMAC1_CLK_RES_CTRL, 0, BIT(1)),
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[RESET_JPG] = RESET_DATA(APMU_JPG_CLK_RES_CTRL, 0, BIT(0)),
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[RESET_CCIC2PHY] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(2)),
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[RESET_CCIC3PHY] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(29)),
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[RESET_CSI] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(1)),
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[RESET_ISP] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(0)),
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[RESET_ISP_CPP] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(27)),
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[RESET_ISP_BUS] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(3)),
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[RESET_ISP_CI] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(16)),
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[RESET_DPU_MCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL2, 0, BIT(9)),
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[RESET_DPU_ESC] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(3)),
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[RESET_DPU_HCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(4)),
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[RESET_DPU_SPIBUS] = RESET_DATA(APMU_LCD_SPI_CLK_RES_CTRL, 0, BIT(4)),
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[RESET_DPU_SPI_HBUS] = RESET_DATA(APMU_LCD_SPI_CLK_RES_CTRL, 0, BIT(2)),
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[RESET_V2D] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(27)),
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[RESET_MIPI] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(15)),
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[RESET_MC] = RESET_DATA(APMU_PMUA_MC_CTRL, 0, BIT(0)),
162+
};
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static const struct ccu_reset_controller_data k1_apmu_reset_data = {
165+
.reset_data = k1_apmu_resets,
166+
.count = ARRAY_SIZE(k1_apmu_resets),
167+
};
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static const struct ccu_reset_data k1_rcpu_resets[] = {
170+
[RESET_RCPU_SSP0] = RESET_DATA(RCPU_SSP0_CLK_RST, 0, BIT(0)),
171+
[RESET_RCPU_I2C0] = RESET_DATA(RCPU_I2C0_CLK_RST, 0, BIT(0)),
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[RESET_RCPU_UART1] = RESET_DATA(RCPU_UART1_CLK_RST, 0, BIT(0)),
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[RESET_RCPU_IR] = RESET_DATA(RCPU_CAN_CLK_RST, 0, BIT(0)),
174+
[RESET_RCPU_CAN] = RESET_DATA(RCPU_IR_CLK_RST, 0, BIT(0)),
175+
[RESET_RCPU_UART0] = RESET_DATA(RCPU_UART0_CLK_RST, 0, BIT(0)),
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[RESET_RCPU_HDMI_AUDIO] = RESET_DATA(AUDIO_HDMI_CLK_CTRL, 0, BIT(0)),
177+
};
178+
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static const struct ccu_reset_controller_data k1_rcpu_reset_data = {
180+
.reset_data = k1_rcpu_resets,
181+
.count = ARRAY_SIZE(k1_rcpu_resets),
182+
};
183+
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static const struct ccu_reset_data k1_rcpu2_resets[] = {
185+
[RESET_RCPU2_PWM0] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
186+
[RESET_RCPU2_PWM1] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
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[RESET_RCPU2_PWM2] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
188+
[RESET_RCPU2_PWM3] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
189+
[RESET_RCPU2_PWM4] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
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[RESET_RCPU2_PWM5] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
191+
[RESET_RCPU2_PWM6] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
192+
[RESET_RCPU2_PWM7] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
193+
[RESET_RCPU2_PWM8] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
194+
[RESET_RCPU2_PWM9] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
195+
};
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static const struct ccu_reset_controller_data k1_rcpu2_reset_data = {
198+
.reset_data = k1_rcpu2_resets,
199+
.count = ARRAY_SIZE(k1_rcpu2_resets),
200+
};
201+
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static const struct ccu_reset_data k1_apbc2_resets[] = {
203+
[RESET_APBC2_UART1] = RESET_DATA(APBC2_UART1_CLK_RST, BIT(2), 0),
204+
[RESET_APBC2_SSP2] = RESET_DATA(APBC2_SSP2_CLK_RST, BIT(2), 0),
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[RESET_APBC2_TWSI3] = RESET_DATA(APBC2_TWSI3_CLK_RST, BIT(2), 0),
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[RESET_APBC2_RTC] = RESET_DATA(APBC2_RTC_CLK_RST, BIT(2), 0),
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[RESET_APBC2_TIMERS0] = RESET_DATA(APBC2_TIMERS0_CLK_RST, BIT(2), 0),
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[RESET_APBC2_KPC] = RESET_DATA(APBC2_KPC_CLK_RST, BIT(2), 0),
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[RESET_APBC2_GPIO] = RESET_DATA(APBC2_GPIO_CLK_RST, BIT(2), 0),
210+
};
211+
212+
static const struct ccu_reset_controller_data k1_apbc2_reset_data = {
213+
.reset_data = k1_apbc2_resets,
214+
.count = ARRAY_SIZE(k1_apbc2_resets),
215+
};
216+
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static int spacemit_reset_update(struct reset_controller_dev *rcdev,
218+
unsigned long id, bool assert)
219+
{
220+
struct ccu_reset_controller *controller;
221+
const struct ccu_reset_data *data;
222+
u32 mask;
223+
u32 val;
224+
225+
controller = container_of(rcdev, struct ccu_reset_controller, rcdev);
226+
data = &controller->data->reset_data[id];
227+
mask = data->assert_mask | data->deassert_mask;
228+
val = assert ? data->assert_mask : data->deassert_mask;
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return regmap_update_bits(controller->regmap, data->offset, mask, val);
231+
}
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static int spacemit_reset_assert(struct reset_controller_dev *rcdev,
234+
unsigned long id)
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{
236+
return spacemit_reset_update(rcdev, id, true);
237+
}
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static int spacemit_reset_deassert(struct reset_controller_dev *rcdev,
240+
unsigned long id)
241+
{
242+
return spacemit_reset_update(rcdev, id, false);
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}
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static const struct reset_control_ops spacemit_reset_control_ops = {
246+
.assert = spacemit_reset_assert,
247+
.deassert = spacemit_reset_deassert,
248+
};
249+
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static int spacemit_reset_controller_register(struct device *dev,
251+
struct ccu_reset_controller *controller)
252+
{
253+
struct reset_controller_dev *rcdev = &controller->rcdev;
254+
255+
rcdev->ops = &spacemit_reset_control_ops;
256+
rcdev->owner = THIS_MODULE;
257+
rcdev->of_node = dev->of_node;
258+
rcdev->nr_resets = controller->data->count;
259+
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return devm_reset_controller_register(dev, &controller->rcdev);
261+
}
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static int spacemit_reset_probe(struct auxiliary_device *adev,
264+
const struct auxiliary_device_id *id)
265+
{
266+
struct spacemit_ccu_adev *rdev = to_spacemit_ccu_adev(adev);
267+
struct ccu_reset_controller *controller;
268+
struct device *dev = &adev->dev;
269+
270+
controller = devm_kzalloc(dev, sizeof(*controller), GFP_KERNEL);
271+
if (!controller)
272+
return -ENOMEM;
273+
controller->data = (const struct ccu_reset_controller_data *)id->driver_data;
274+
controller->regmap = rdev->regmap;
275+
276+
return spacemit_reset_controller_register(dev, controller);
277+
}
278+
279+
#define K1_AUX_DEV_ID(_unit) \
280+
{ \
281+
.name = "spacemit_ccu_k1." #_unit "-reset", \
282+
.driver_data = (kernel_ulong_t)&k1_ ## _unit ## _reset_data, \
283+
}
284+
285+
static const struct auxiliary_device_id spacemit_reset_ids[] = {
286+
K1_AUX_DEV_ID(mpmu),
287+
K1_AUX_DEV_ID(apbc),
288+
K1_AUX_DEV_ID(apmu),
289+
K1_AUX_DEV_ID(rcpu),
290+
K1_AUX_DEV_ID(rcpu2),
291+
K1_AUX_DEV_ID(apbc2),
292+
{ },
293+
};
294+
MODULE_DEVICE_TABLE(auxiliary, spacemit_reset_ids);
295+
296+
static struct auxiliary_driver spacemit_k1_reset_driver = {
297+
.probe = spacemit_reset_probe,
298+
.id_table = spacemit_reset_ids,
299+
};
300+
module_auxiliary_driver(spacemit_k1_reset_driver);
301+
302+
MODULE_AUTHOR("Alex Elder <[email protected]>");
303+
MODULE_DESCRIPTION("SpacemiT reset controller driver");
304+
MODULE_LICENSE("GPL");

‎include/soc/spacemit/k1-syscon.h

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -127,4 +127,34 @@ to_spacemit_ccu_adev(struct auxiliary_device *adev)
127127
#define APMU_EMAC0_CLK_RES_CTRL 0x3e4
128128
#define APMU_EMAC1_CLK_RES_CTRL 0x3ec
129129

130+
/* RCPU register offsets */
131+
#define RCPU_SSP0_CLK_RST 0x0028
132+
#define RCPU_I2C0_CLK_RST 0x0030
133+
#define RCPU_UART1_CLK_RST 0x003c
134+
#define RCPU_CAN_CLK_RST 0x0048
135+
#define RCPU_IR_CLK_RST 0x004c
136+
#define RCPU_UART0_CLK_RST 0x00d8
137+
#define AUDIO_HDMI_CLK_CTRL 0x2044
138+
139+
/* RCPU2 register offsets */
140+
#define RCPU2_PWM0_CLK_RST 0x0000
141+
#define RCPU2_PWM1_CLK_RST 0x0004
142+
#define RCPU2_PWM2_CLK_RST 0x0008
143+
#define RCPU2_PWM3_CLK_RST 0x000c
144+
#define RCPU2_PWM4_CLK_RST 0x0010
145+
#define RCPU2_PWM5_CLK_RST 0x0014
146+
#define RCPU2_PWM6_CLK_RST 0x0018
147+
#define RCPU2_PWM7_CLK_RST 0x001c
148+
#define RCPU2_PWM8_CLK_RST 0x0020
149+
#define RCPU2_PWM9_CLK_RST 0x0024
150+
151+
/* APBC2 register offsets */
152+
#define APBC2_UART1_CLK_RST 0x0000
153+
#define APBC2_SSP2_CLK_RST 0x0004
154+
#define APBC2_TWSI3_CLK_RST 0x0008
155+
#define APBC2_RTC_CLK_RST 0x000c
156+
#define APBC2_TIMERS0_CLK_RST 0x0010
157+
#define APBC2_KPC_CLK_RST 0x0014
158+
#define APBC2_GPIO_CLK_RST 0x001c
159+
130160
#endif /* __SOC_K1_SYSCON_H__ */

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