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| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | +%YAML 1.2 |
| 3 | +--- |
| 4 | +$id: http://devicetree.org/schemas/clock/marvell,armada-3700-periph-clock.yaml# |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | + |
| 7 | +title: Marvell Armada 37xx SoCs Peripheral Clocks |
| 8 | + |
| 9 | +maintainers: |
| 10 | + |
| 11 | + - Gregory Clement <[email protected]> |
| 12 | + |
| 13 | +description: > |
| 14 | + Marvell Armada 37xx SoCs provide peripheral clocks which are used as clock |
| 15 | + source for the peripheral of the SoC. |
| 16 | +
|
| 17 | + There are two different blocks associated to north bridge and south bridge. |
| 18 | +
|
| 19 | + The following is a list of provided IDs for Armada 3700 North bridge clocks: |
| 20 | +
|
| 21 | + ID Clock name Description |
| 22 | + ----------------------------------- |
| 23 | + 0 mmc MMC controller |
| 24 | + 1 sata_host Sata Host |
| 25 | + 2 sec_at Security AT |
| 26 | + 3 sac_dap Security DAP |
| 27 | + 4 tsecm Security Engine |
| 28 | + 5 setm_tmx Serial Embedded Trace Module |
| 29 | + 6 avs Adaptive Voltage Scaling |
| 30 | + 7 sqf SPI |
| 31 | + 8 pwm PWM |
| 32 | + 9 i2c_2 I2C 2 |
| 33 | + 10 i2c_1 I2C 1 |
| 34 | + 11 ddr_phy DDR PHY |
| 35 | + 12 ddr_fclk DDR F clock |
| 36 | + 13 trace Trace |
| 37 | + 14 counter Counter |
| 38 | + 15 eip97 EIP 97 |
| 39 | + 16 cpu CPU |
| 40 | +
|
| 41 | + The following is a list of provided IDs for Armada 3700 South bridge clocks: |
| 42 | +
|
| 43 | + ID Clock name Description |
| 44 | + ----------------------------------- |
| 45 | + 0 gbe-50 50 MHz parent clock for Gigabit Ethernet |
| 46 | + 1 gbe-core parent clock for Gigabit Ethernet core |
| 47 | + 2 gbe-125 125 MHz parent clock for Gigabit Ethernet |
| 48 | + 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1 |
| 49 | + 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0 |
| 50 | + 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1 |
| 51 | + 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0 |
| 52 | + 7 gbe1-core Gigabit Ethernet core port 1 |
| 53 | + 8 gbe0-core Gigabit Ethernet core port 0 |
| 54 | + 9 gbe-bm Gigabit Ethernet Buffer Manager |
| 55 | + 10 sdio SDIO |
| 56 | + 11 usb32-sub2-sys USB 2 clock |
| 57 | + 12 usb32-ss-sys USB 3 clock |
| 58 | + 13 pcie PCIe controller |
| 59 | +
|
| 60 | +properties: |
| 61 | + compatible: |
| 62 | + oneOf: |
| 63 | + - const: marvell,armada-3700-periph-clock-sb |
| 64 | + - items: |
| 65 | + - const: marvell,armada-3700-periph-clock-nb |
| 66 | + - const: syscon |
| 67 | + reg: |
| 68 | + maxItems: 1 |
| 69 | + |
| 70 | + clocks: |
| 71 | + items: |
| 72 | + - description: TBG-A P clock and specifier |
| 73 | + - description: TBG-B P clock and specifier |
| 74 | + - description: TBG-A S clock and specifier |
| 75 | + - description: TBG-B S clock and specifier |
| 76 | + - description: Xtal clock and specifier |
| 77 | + |
| 78 | + '#clock-cells': |
| 79 | + const: 1 |
| 80 | + |
| 81 | +required: |
| 82 | + - compatible |
| 83 | + - reg |
| 84 | + - clocks |
| 85 | + - '#clock-cells' |
| 86 | + |
| 87 | +additionalProperties: false |
| 88 | + |
| 89 | +examples: |
| 90 | + - | |
| 91 | + clock-controller@13000{ |
| 92 | + compatible = "marvell,armada-3700-periph-clock-sb"; |
| 93 | + reg = <0x13000 0x1000>; |
| 94 | + clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>, <&xtalclk>; |
| 95 | + #clock-cells = <1>; |
| 96 | + }; |
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