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Merge branch 'for-6.17/dt-bindings' into for-6.17/arm64/dt
2 parents 19272b3 + 0b22638 commit f1358b1

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‎Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml

Lines changed: 82 additions & 2 deletions
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@@ -32,6 +32,7 @@ properties:
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- nvidia,tegra186-mc
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- nvidia,tegra194-mc
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- nvidia,tegra234-mc
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- nvidia,tegra264-mc
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reg:
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minItems: 6
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maxItems: 18
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interrupts:
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items:
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- description: MC general interrupt
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minItems: 1
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maxItems: 8
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interrupt-names:
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minItems: 1
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maxItems: 8
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"#address-cells":
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const: 2
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- nvidia,tegra186-emc
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- nvidia,tegra194-emc
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- nvidia,tegra234-emc
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- nvidia,tegra264-emc
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reg:
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minItems: 1
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reg:
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minItems: 2
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- if:
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properties:
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compatible:
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const: nvidia,tegra264-emc
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then:
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properties:
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reg:
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minItems: 2
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additionalProperties: false
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required:
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- const: ch2
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- const: ch3
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interrupts:
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items:
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- description: MC general interrupt
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interrupt-names: false
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- if:
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properties:
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compatible:
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- const: ch14
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- const: ch15
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interrupts:
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items:
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- description: MC general interrupt
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interrupt-names: false
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- if:
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properties:
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compatible:
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- const: ch14
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- const: ch15
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interrupts:
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items:
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- description: MC general interrupt
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interrupt-names: false
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- if:
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properties:
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compatible:
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const: nvidia,tegra264-mc
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then:
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properties:
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reg:
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minItems: 17
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maxItems: 17
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description: 17 memory controller channels
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reg-names:
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items:
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- const: broadcast
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- const: ch0
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- const: ch1
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- const: ch2
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- const: ch3
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- const: ch4
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- const: ch5
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- const: ch6
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- const: ch7
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- const: ch8
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- const: ch9
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- const: ch10
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- const: ch11
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- const: ch12
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- const: ch13
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- const: ch14
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- const: ch15
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interrupts:
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minItems: 8
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maxItems: 8
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description: One interrupt line for each MC component
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interrupt-names:
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items:
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- const: mcf
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- const: hub1
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- const: hub2
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- const: hub3
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- const: hub4
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- const: hub5
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- const: sbs
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- const: channel
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additionalProperties: false
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required:

‎include/dt-bindings/memory/nvidia,tegra264.h

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@@ -0,0 +1,136 @@
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. */
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#ifndef DT_BINDINGS_MEMORY_NVIDIA_TEGRA264_H
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#define DT_BINDINGS_MEMORY_NVIDIA_TEGRA264_H
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#define TEGRA264_SID(x) ((x) << 8)
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/*
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* SMMU stream IDs
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*/
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#define TEGRA264_SID_AON TEGRA264_SID(0x01)
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#define TEGRA264_SID_APE TEGRA264_SID(0x02)
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#define TEGRA264_SID_ETR TEGRA264_SID(0x03)
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#define TEGRA264_SID_BPMP TEGRA264_SID(0x04)
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#define TEGRA264_SID_DCE TEGRA264_SID(0x05)
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#define TEGRA264_SID_EQOS TEGRA264_SID(0x06)
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#define TEGRA264_SID_GPCDMA TEGRA264_SID(0x08)
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#define TEGRA264_SID_DISP TEGRA264_SID(0x09)
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#define TEGRA264_SID_HDA TEGRA264_SID(0x0a)
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#define TEGRA264_SID_HOST1X TEGRA264_SID(0x0b)
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#define TEGRA264_SID_ISP0 TEGRA264_SID(0x0c)
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#define TEGRA264_SID_ISP1 TEGRA264_SID(0x0d)
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#define TEGRA264_SID_PMA0 TEGRA264_SID(0x0e)
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#define TEGRA264_SID_FSI0 TEGRA264_SID(0x0f)
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#define TEGRA264_SID_FSI1 TEGRA264_SID(0x10)
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#define TEGRA264_SID_PVA TEGRA264_SID(0x11)
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#define TEGRA264_SID_SDMMC0 TEGRA264_SID(0x12)
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#define TEGRA264_SID_MGBE0 TEGRA264_SID(0x13)
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#define TEGRA264_SID_MGBE1 TEGRA264_SID(0x14)
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#define TEGRA264_SID_MGBE2 TEGRA264_SID(0x15)
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#define TEGRA264_SID_MGBE3 TEGRA264_SID(0x16)
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#define TEGRA264_SID_MSSSEQ TEGRA264_SID(0x17)
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#define TEGRA264_SID_SE TEGRA264_SID(0x18)
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#define TEGRA264_SID_SEU1 TEGRA264_SID(0x19)
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#define TEGRA264_SID_SEU2 TEGRA264_SID(0x1a)
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#define TEGRA264_SID_SEU3 TEGRA264_SID(0x1b)
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#define TEGRA264_SID_PSC TEGRA264_SID(0x1c)
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#define TEGRA264_SID_OESP TEGRA264_SID(0x23)
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#define TEGRA264_SID_SB TEGRA264_SID(0x24)
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#define TEGRA264_SID_XSPI0 TEGRA264_SID(0x25)
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#define TEGRA264_SID_TSEC TEGRA264_SID(0x29)
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#define TEGRA264_SID_UFS TEGRA264_SID(0x2a)
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#define TEGRA264_SID_RCE TEGRA264_SID(0x2b)
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#define TEGRA264_SID_RCE1 TEGRA264_SID(0x2c)
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#define TEGRA264_SID_VI TEGRA264_SID(0x2e)
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#define TEGRA264_SID_VI1 TEGRA264_SID(0x2f)
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#define TEGRA264_SID_VIC TEGRA264_SID(0x30)
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#define TEGRA264_SID_XUSB_DEV TEGRA264_SID(0x32)
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#define TEGRA264_SID_XUSB_DEV1 TEGRA264_SID(0x33)
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#define TEGRA264_SID_XUSB_DEV2 TEGRA264_SID(0x34)
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#define TEGRA264_SID_XUSB_DEV3 TEGRA264_SID(0x35)
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#define TEGRA264_SID_XUSB_DEV4 TEGRA264_SID(0x36)
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#define TEGRA264_SID_XUSB_DEV5 TEGRA264_SID(0x37)
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/*
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* memory client IDs
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*/
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/* HOST1X read client */
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#define TEGRA264_MEMORY_CLIENT_HOST1XR 0x16
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/* VIC read client */
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#define TEGRA264_MEMORY_CLIENT_VICR 0x6c
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/* VIC Write client */
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#define TEGRA264_MEMORY_CLIENT_VICW 0x6d
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/* VI R5 Write client */
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#define TEGRA264_MEMORY_CLIENT_VIW 0x72
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#define TEGRA264_MEMORY_CLIENT_NVDECSRD2MC 0x78
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#define TEGRA264_MEMORY_CLIENT_NVDECSWR2MC 0x79
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/* Audio processor(APE) Read client */
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#define TEGRA264_MEMORY_CLIENT_APER 0x7a
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/* Audio processor(APE) Write client */
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#define TEGRA264_MEMORY_CLIENT_APEW 0x7b
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/* Audio DMA Read client */
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#define TEGRA264_MEMORY_CLIENT_APEDMAR 0x9f
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/* Audio DMA Write client */
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#define TEGRA264_MEMORY_CLIENT_APEDMAW 0xa0
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#define TEGRA264_MEMORY_CLIENT_GPUR02MC 0xb6
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#define TEGRA264_MEMORY_CLIENT_GPUW02MC 0xb7
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/* VI Falcon Read client */
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#define TEGRA264_MEMORY_CLIENT_VIFALCONR 0xbc
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/* VI Falcon Write client */
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#define TEGRA264_MEMORY_CLIENT_VIFALCONW 0xbd
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/* Read Client of RCE */
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#define TEGRA264_MEMORY_CLIENT_RCER 0xd2
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/* Write client of RCE */
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#define TEGRA264_MEMORY_CLIENT_RCEW 0xd3
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/* PCIE0/MSI Write clients */
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#define TEGRA264_MEMORY_CLIENT_PCIE0W 0xd9
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/* PCIE1/RPX4 Read clients */
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#define TEGRA264_MEMORY_CLIENT_PCIE1R 0xda
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/* PCIE1/RPX4 Write clients */
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#define TEGRA264_MEMORY_CLIENT_PCIE1W 0xdb
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/* PCIE2/DMX4 Read clients */
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#define TEGRA264_MEMORY_CLIENT_PCIE2AR 0xdc
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/* PCIE2/DMX4 Write clients */
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#define TEGRA264_MEMORY_CLIENT_PCIE2AW 0xdd
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/* PCIE3/RPX4 Read clients */
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#define TEGRA264_MEMORY_CLIENT_PCIE3R 0xde
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/* PCIE3/RPX4 Write clients */
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#define TEGRA264_MEMORY_CLIENT_PCIE3W 0xdf
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/* PCIE4/DMX8 Read clients */
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#define TEGRA264_MEMORY_CLIENT_PCIE4R 0xe0
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/* PCIE4/DMX8 Write clients */
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#define TEGRA264_MEMORY_CLIENT_PCIE4W 0xe1
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/* PCIE5/DMX4 Read clients */
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#define TEGRA264_MEMORY_CLIENT_PCIE5R 0xe2
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/* PCIE5/DMX4 Write clients */
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#define TEGRA264_MEMORY_CLIENT_PCIE5W 0xe3
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/* UFS Read client */
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#define TEGRA264_MEMORY_CLIENT_UFSR 0x15c
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/* UFS write client */
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#define TEGRA264_MEMORY_CLIENT_UFSW 0x15d
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/* HDA Read client */
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#define TEGRA264_MEMORY_CLIENT_HDAR 0x17c
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/* HDA Write client */
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#define TEGRA264_MEMORY_CLIENT_HDAW 0x17d
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/* Disp ISO Read Client */
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#define TEGRA264_MEMORY_CLIENT_DISPR 0x182
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/* MGBE0 Read mccif */
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#define TEGRA264_MEMORY_CLIENT_MGBE0R 0x1a2
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/* MGBE0 Write mccif */
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#define TEGRA264_MEMORY_CLIENT_MGBE0W 0x1a3
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/* MGBE1 Read mccif */
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#define TEGRA264_MEMORY_CLIENT_MGBE1R 0x1a4
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/* MGBE1 Write mccif */
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#define TEGRA264_MEMORY_CLIENT_MGBE1W 0x1a5
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/* VI1 R5 Write client */
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#define TEGRA264_MEMORY_CLIENT_VI1W 0x1a6
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/* SDMMC0 Read mccif */
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#define TEGRA264_MEMORY_CLIENT_SDMMC0R 0x1c2
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/* SDMMC0 Write mccif */
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#define TEGRA264_MEMORY_CLIENT_SDMMC0W 0x1c3
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#endif /* DT_BINDINGS_MEMORY_NVIDIA_TEGRA264_H */

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