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ukleinekUwe Kleine-König
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pwm: mediatek: Fix duty and period setting
The period generated by the hardware is (PWMDWIDTH + 1) << CLKDIV) / freq according to my tests with a signal analyser and also the documentation. The current algorithm doesn't consider the `+ 1` part and so configures slightly too high periods. The same issue exists for the duty cycle setting. So subtract 1 from both the register values for period and duty cycle. If period is 0, bail out, if duty_cycle is 0, just disable the PWM which results in a constant low output. Fixes: caf065f ("pwm: Add MediaTek PWM support") Signed-off-by: Uwe Kleine-König <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/6d1fa87a76f8020bfe3171529b8e19baffceab10.1753717973.git.u.kleine-koenig@baylibre.com Cc: [email protected] Signed-off-by: Uwe Kleine-König <[email protected]>
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drivers/pwm/pwm-mediatek.c

Lines changed: 14 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -170,7 +170,10 @@ static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
170170
do_div(resolution, clk_rate);
171171

172172
cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution);
173-
while (cnt_period > 8191) {
173+
if (!cnt_period)
174+
return -EINVAL;
175+
176+
while (cnt_period > 8192) {
174177
resolution *= 2;
175178
clkdiv++;
176179
cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000,
@@ -193,9 +196,16 @@ static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
193196
}
194197

195198
cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution);
199+
196200
pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
197-
pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period);
198-
pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty);
201+
pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period - 1);
202+
203+
if (cnt_duty) {
204+
pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty - 1);
205+
pwm_mediatek_enable(chip, pwm);
206+
} else {
207+
pwm_mediatek_disable(chip, pwm);
208+
}
199209

200210
out:
201211
pwm_mediatek_clk_disable(chip, pwm);
@@ -224,11 +234,8 @@ static int pwm_mediatek_apply(struct pwm_chip *chip, struct pwm_device *pwm,
224234
if (err)
225235
return err;
226236

227-
if (!pwm->state.enabled) {
237+
if (!pwm->state.enabled)
228238
err = pwm_mediatek_clk_enable(chip, pwm);
229-
if (!err)
230-
pwm_mediatek_enable(chip, pwm);
231-
}
232239

233240
return err;
234241
}

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