@@ -9050,21 +9050,6 @@ static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
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ref , mask );
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}
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- static void gfx_v10_0_ring_soft_recovery (struct amdgpu_ring * ring ,
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- unsigned int vmid )
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- {
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- struct amdgpu_device * adev = ring -> adev ;
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- uint32_t value = 0 ;
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-
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- value = REG_SET_FIELD (value , SQ_CMD , CMD , 0x03 );
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- value = REG_SET_FIELD (value , SQ_CMD , MODE , 0x01 );
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- value = REG_SET_FIELD (value , SQ_CMD , CHECK_VMID , 1 );
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- value = REG_SET_FIELD (value , SQ_CMD , VM_ID , vmid );
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- amdgpu_gfx_rlc_enter_safe_mode (adev , 0 );
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- WREG32_SOC15 (GC , 0 , mmSQ_CMD , value );
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- amdgpu_gfx_rlc_exit_safe_mode (adev , 0 );
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- }
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-
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static void
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gfx_v10_0_set_gfx_eop_interrupt_state (struct amdgpu_device * adev ,
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uint32_t me , uint32_t pipe ,
@@ -9544,7 +9529,7 @@ static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring,
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if (!kiq -> pmf || !kiq -> pmf -> kiq_unmap_queues )
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return - EINVAL ;
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- drm_sched_wqueue_stop ( & ring -> sched );
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+ amdgpu_ring_reset_helper_begin ( ring , timedout_fence );
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spin_lock_irqsave (& kiq -> ring_lock , flags );
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@@ -9593,12 +9578,7 @@ static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring,
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if (r )
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return r ;
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- r = amdgpu_ring_test_ring (ring );
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- if (r )
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- return r ;
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- amdgpu_fence_driver_force_completion (ring );
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- drm_sched_wqueue_start (& ring -> sched );
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- return 0 ;
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+ return amdgpu_ring_reset_helper_end (ring , timedout_fence );
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}
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static int gfx_v10_0_reset_kcq (struct amdgpu_ring * ring ,
@@ -9617,7 +9597,7 @@ static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring,
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if (!kiq -> pmf || !kiq -> pmf -> kiq_unmap_queues )
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return - EINVAL ;
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- drm_sched_wqueue_stop ( & ring -> sched );
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+ amdgpu_ring_reset_helper_begin ( ring , timedout_fence );
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spin_lock_irqsave (& kiq -> ring_lock , flags );
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@@ -9671,12 +9651,7 @@ static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring,
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if (r )
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return r ;
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- r = amdgpu_ring_test_ring (ring );
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- if (r )
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- return r ;
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- amdgpu_fence_driver_force_completion (ring );
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- drm_sched_wqueue_start (& ring -> sched );
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- return 0 ;
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+ return amdgpu_ring_reset_helper_end (ring , timedout_fence );
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}
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static void gfx_v10_ip_print (struct amdgpu_ip_block * ip_block , struct drm_printer * p )
@@ -9911,7 +9886,6 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
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.emit_wreg = gfx_v10_0_ring_emit_wreg ,
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.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait ,
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.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait ,
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- .soft_recovery = gfx_v10_0_ring_soft_recovery ,
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.emit_mem_sync = gfx_v10_0_emit_mem_sync ,
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.reset = gfx_v10_0_reset_kgq ,
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.emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader ,
@@ -9952,7 +9926,6 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
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.emit_wreg = gfx_v10_0_ring_emit_wreg ,
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.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait ,
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.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait ,
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- .soft_recovery = gfx_v10_0_ring_soft_recovery ,
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.emit_mem_sync = gfx_v10_0_emit_mem_sync ,
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.reset = gfx_v10_0_reset_kcq ,
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.emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader ,
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