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Sam Protsenkokrzk
Sam Protsenko
authored and
krzk
committed
clk: samsung: exynos850: Implement CMU_MFCMSCL domain
CMU_MFCMSCL clock domain provides clocks for MFC (Multi-Format Codec), JPEG Codec and Scaler IP-cores. According to Exynos850 TRM, CMU_MFCMSCL generates MFC, M2M, MCSC and JPEG clocks for BLK_MFCMSCL. This patch adds next clocks: - bus clocks in CMU_TOP for CMU_MFCMSCL - all internal CMU_MFCMSCL clocks - leaf clocks for MFCMSCL, TZPC (TrustZone Protection Controller), JPEG codec, M2M (Memory-to-Memory), MCSC (Multi-Channel Scaler), MFC (Multi-Format Codec), PPMU (Platform Performance Monitoring Unit), SysMMU and SysReg MFCMSCL related gate clocks in CMU_TOP were marked as CLK_IS_CRITICAL, because: 1. All of those have to be enabled in order to read /sys/kernel/debug/clk/clk_summary file 2. When some user driver (e.g. exynos-sysmmu) disables some derived leaf clock, it can lead to CMU_TOP clocks disable, which then makes the system hang. To prevent that, the CLK_IS_CRITICAL flag is used, as CLK_IGNORE_UNUSED is not enough. Signed-off-by: Sam Protsenko <[email protected]> Acked-by: Chanwoo Choi <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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‎drivers/clk/samsung/clk-exynos850.c‎

Lines changed: 176 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -43,6 +43,10 @@
4343
#define CLK_CON_MUX_MUX_CLKCMU_IS_GDC 0x104c
4444
#define CLK_CON_MUX_MUX_CLKCMU_IS_ITP 0x1050
4545
#define CLK_CON_MUX_MUX_CLKCMU_IS_VRA 0x1054
46+
#define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG 0x1058
47+
#define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M 0x105c
48+
#define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC 0x1060
49+
#define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC 0x1064
4650
#define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070
4751
#define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074
4852
#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078
@@ -60,6 +64,10 @@
6064
#define CLK_CON_DIV_CLKCMU_IS_GDC 0x1858
6165
#define CLK_CON_DIV_CLKCMU_IS_ITP 0x185c
6266
#define CLK_CON_DIV_CLKCMU_IS_VRA 0x1860
67+
#define CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG 0x1864
68+
#define CLK_CON_DIV_CLKCMU_MFCMSCL_M2M 0x1868
69+
#define CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC 0x186c
70+
#define CLK_CON_DIV_CLKCMU_MFCMSCL_MFC 0x1870
6371
#define CLK_CON_DIV_CLKCMU_PERI_BUS 0x187c
6472
#define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880
6573
#define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884
@@ -83,6 +91,10 @@
8391
#define CLK_CON_GAT_GATE_CLKCMU_IS_GDC 0x2054
8492
#define CLK_CON_GAT_GATE_CLKCMU_IS_ITP 0x2058
8593
#define CLK_CON_GAT_GATE_CLKCMU_IS_VRA 0x205c
94+
#define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG 0x2060
95+
#define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M 0x2064
96+
#define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC 0x2068
97+
#define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC 0x206c
8698
#define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080
8799
#define CLK_CON_GAT_GATE_CLKCMU_PERI_IP 0x2084
88100
#define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088
@@ -111,6 +123,10 @@ static const unsigned long top_clk_regs[] __initconst = {
111123
CLK_CON_MUX_MUX_CLKCMU_IS_GDC,
112124
CLK_CON_MUX_MUX_CLKCMU_IS_ITP,
113125
CLK_CON_MUX_MUX_CLKCMU_IS_VRA,
126+
CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG,
127+
CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M,
128+
CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC,
129+
CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC,
114130
CLK_CON_MUX_MUX_CLKCMU_PERI_BUS,
115131
CLK_CON_MUX_MUX_CLKCMU_PERI_IP,
116132
CLK_CON_MUX_MUX_CLKCMU_PERI_UART,
@@ -128,6 +144,10 @@ static const unsigned long top_clk_regs[] __initconst = {
128144
CLK_CON_DIV_CLKCMU_IS_GDC,
129145
CLK_CON_DIV_CLKCMU_IS_ITP,
130146
CLK_CON_DIV_CLKCMU_IS_VRA,
147+
CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG,
148+
CLK_CON_DIV_CLKCMU_MFCMSCL_M2M,
149+
CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC,
150+
CLK_CON_DIV_CLKCMU_MFCMSCL_MFC,
131151
CLK_CON_DIV_CLKCMU_PERI_BUS,
132152
CLK_CON_DIV_CLKCMU_PERI_IP,
133153
CLK_CON_DIV_CLKCMU_PERI_UART,
@@ -151,6 +171,10 @@ static const unsigned long top_clk_regs[] __initconst = {
151171
CLK_CON_GAT_GATE_CLKCMU_IS_GDC,
152172
CLK_CON_GAT_GATE_CLKCMU_IS_ITP,
153173
CLK_CON_GAT_GATE_CLKCMU_IS_VRA,
174+
CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG,
175+
CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M,
176+
CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC,
177+
CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC,
154178
CLK_CON_GAT_GATE_CLKCMU_PERI_BUS,
155179
CLK_CON_GAT_GATE_CLKCMU_PERI_IP,
156180
CLK_CON_GAT_GATE_CLKCMU_PERI_UART,
@@ -209,6 +233,15 @@ PNAME(mout_is_vra_p) = { "dout_shared0_div2", "dout_shared1_div2",
209233
"dout_shared0_div3", "dout_shared1_div3" };
210234
PNAME(mout_is_gdc_p) = { "dout_shared0_div2", "dout_shared1_div2",
211235
"dout_shared0_div3", "dout_shared1_div3" };
236+
/* List of parent clocks for Muxes in CMU_TOP: for CMU_MFCMSCL */
237+
PNAME(mout_mfcmscl_mfc_p) = { "dout_shared1_div2", "dout_shared0_div3",
238+
"dout_shared1_div3", "dout_shared0_div4" };
239+
PNAME(mout_mfcmscl_m2m_p) = { "dout_shared1_div2", "dout_shared0_div3",
240+
"dout_shared1_div3", "dout_shared0_div4" };
241+
PNAME(mout_mfcmscl_mcsc_p) = { "dout_shared1_div2", "dout_shared0_div3",
242+
"dout_shared1_div3", "dout_shared0_div4" };
243+
PNAME(mout_mfcmscl_jpeg_p) = { "dout_shared0_div3", "dout_shared1_div3",
244+
"dout_shared0_div4", "dout_shared1_div4" };
212245
/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */
213246
PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" };
214247
PNAME(mout_peri_uart_p) = { "oscclk", "dout_shared0_div4",
@@ -268,6 +301,16 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
268301
MUX(CLK_MOUT_IS_GDC, "mout_is_gdc", mout_is_gdc_p,
269302
CLK_CON_MUX_MUX_CLKCMU_IS_GDC, 0, 2),
270303

304+
/* MFCMSCL */
305+
MUX(CLK_MOUT_MFCMSCL_MFC, "mout_mfcmscl_mfc", mout_mfcmscl_mfc_p,
306+
CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC, 0, 2),
307+
MUX(CLK_MOUT_MFCMSCL_M2M, "mout_mfcmscl_m2m", mout_mfcmscl_m2m_p,
308+
CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M, 0, 2),
309+
MUX(CLK_MOUT_MFCMSCL_MCSC, "mout_mfcmscl_mcsc", mout_mfcmscl_mcsc_p,
310+
CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC, 0, 2),
311+
MUX(CLK_MOUT_MFCMSCL_JPEG, "mout_mfcmscl_jpeg", mout_mfcmscl_jpeg_p,
312+
CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG, 0, 2),
313+
271314
/* PERI */
272315
MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p,
273316
CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1),
@@ -332,6 +375,16 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
332375
DIV(CLK_DOUT_IS_GDC, "dout_is_gdc", "gout_is_gdc",
333376
CLK_CON_DIV_CLKCMU_IS_GDC, 0, 4),
334377

378+
/* MFCMSCL */
379+
DIV(CLK_DOUT_MFCMSCL_MFC, "dout_mfcmscl_mfc", "gout_mfcmscl_mfc",
380+
CLK_CON_DIV_CLKCMU_MFCMSCL_MFC, 0, 4),
381+
DIV(CLK_DOUT_MFCMSCL_M2M, "dout_mfcmscl_m2m", "gout_mfcmscl_m2m",
382+
CLK_CON_DIV_CLKCMU_MFCMSCL_M2M, 0, 4),
383+
DIV(CLK_DOUT_MFCMSCL_MCSC, "dout_mfcmscl_mcsc", "gout_mfcmscl_mcsc",
384+
CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC, 0, 4),
385+
DIV(CLK_DOUT_MFCMSCL_JPEG, "dout_mfcmscl_jpeg", "gout_mfcmscl_jpeg",
386+
CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG, 0, 4),
387+
335388
/* PERI */
336389
DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus",
337390
CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4),
@@ -383,6 +436,17 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
383436
GATE(CLK_GOUT_IS_GDC, "gout_is_gdc", "mout_is_gdc",
384437
CLK_CON_GAT_GATE_CLKCMU_IS_GDC, 21, CLK_IS_CRITICAL, 0),
385438

439+
/* MFCMSCL */
440+
/* TODO: These have to be always enabled to access CMU_MFCMSCL regs */
441+
GATE(CLK_GOUT_MFCMSCL_MFC, "gout_mfcmscl_mfc", "mout_mfcmscl_mfc",
442+
CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC, 21, CLK_IS_CRITICAL, 0),
443+
GATE(CLK_GOUT_MFCMSCL_M2M, "gout_mfcmscl_m2m", "mout_mfcmscl_m2m",
444+
CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M, 21, CLK_IS_CRITICAL, 0),
445+
GATE(CLK_GOUT_MFCMSCL_MCSC, "gout_mfcmscl_mcsc", "mout_mfcmscl_mcsc",
446+
CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC, 21, CLK_IS_CRITICAL, 0),
447+
GATE(CLK_GOUT_MFCMSCL_JPEG, "gout_mfcmscl_jpeg", "mout_mfcmscl_jpeg",
448+
CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG, 21, CLK_IS_CRITICAL, 0),
449+
386450
/* PERI */
387451
GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus",
388452
CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0),
@@ -1148,6 +1212,115 @@ static const struct samsung_cmu_info is_cmu_info __initconst = {
11481212
.clk_name = "dout_is_bus",
11491213
};
11501214

1215+
/* ---- CMU_MFCMSCL --------------------------------------------------------- */
1216+
1217+
#define PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER 0x0600
1218+
#define PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER 0x0610
1219+
#define PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER 0x0620
1220+
#define PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER 0x0630
1221+
#define CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP 0x1800
1222+
#define CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK 0x2000
1223+
#define CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK 0x2038
1224+
#define CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK 0x203c
1225+
#define CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK 0x2048
1226+
#define CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK 0x204c
1227+
#define CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK 0x2050
1228+
#define CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK 0x2054
1229+
#define CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK 0x2058
1230+
#define CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1 0x2074
1231+
#define CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK 0x2078
1232+
1233+
static const unsigned long mfcmscl_clk_regs[] __initconst = {
1234+
PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER,
1235+
PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER,
1236+
PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER,
1237+
PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER,
1238+
CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP,
1239+
CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK,
1240+
CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK,
1241+
CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK,
1242+
CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK,
1243+
CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK,
1244+
CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK,
1245+
CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK,
1246+
CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK,
1247+
CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1,
1248+
CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK,
1249+
};
1250+
1251+
/* List of parent clocks for Muxes in CMU_MFCMSCL */
1252+
PNAME(mout_mfcmscl_mfc_user_p) = { "oscclk", "dout_mfcmscl_mfc" };
1253+
PNAME(mout_mfcmscl_m2m_user_p) = { "oscclk", "dout_mfcmscl_m2m" };
1254+
PNAME(mout_mfcmscl_mcsc_user_p) = { "oscclk", "dout_mfcmscl_mcsc" };
1255+
PNAME(mout_mfcmscl_jpeg_user_p) = { "oscclk", "dout_mfcmscl_jpeg" };
1256+
1257+
static const struct samsung_mux_clock mfcmscl_mux_clks[] __initconst = {
1258+
MUX(CLK_MOUT_MFCMSCL_MFC_USER, "mout_mfcmscl_mfc_user",
1259+
mout_mfcmscl_mfc_user_p,
1260+
PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER, 4, 1),
1261+
MUX(CLK_MOUT_MFCMSCL_M2M_USER, "mout_mfcmscl_m2m_user",
1262+
mout_mfcmscl_m2m_user_p,
1263+
PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER, 4, 1),
1264+
MUX(CLK_MOUT_MFCMSCL_MCSC_USER, "mout_mfcmscl_mcsc_user",
1265+
mout_mfcmscl_mcsc_user_p,
1266+
PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER, 4, 1),
1267+
MUX(CLK_MOUT_MFCMSCL_JPEG_USER, "mout_mfcmscl_jpeg_user",
1268+
mout_mfcmscl_jpeg_user_p,
1269+
PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER, 4, 1),
1270+
};
1271+
1272+
static const struct samsung_div_clock mfcmscl_div_clks[] __initconst = {
1273+
DIV(CLK_DOUT_MFCMSCL_BUSP, "dout_mfcmscl_busp", "mout_mfcmscl_mfc_user",
1274+
CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP, 0, 3),
1275+
};
1276+
1277+
static const struct samsung_gate_clock mfcmscl_gate_clks[] __initconst = {
1278+
/* TODO: Should be enabled in MFC driver */
1279+
GATE(CLK_GOUT_MFCMSCL_CMU_MFCMSCL_PCLK, "gout_mfcmscl_cmu_mfcmscl_pclk",
1280+
"dout_mfcmscl_busp", CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK,
1281+
21, CLK_IGNORE_UNUSED, 0),
1282+
GATE(CLK_GOUT_MFCMSCL_TZPC_PCLK, "gout_mfcmscl_tzpc_pclk",
1283+
"dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK,
1284+
21, 0, 0),
1285+
GATE(CLK_GOUT_MFCMSCL_JPEG_ACLK, "gout_mfcmscl_jpeg_aclk",
1286+
"mout_mfcmscl_jpeg_user", CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK,
1287+
21, 0, 0),
1288+
GATE(CLK_GOUT_MFCMSCL_M2M_ACLK, "gout_mfcmscl_m2m_aclk",
1289+
"mout_mfcmscl_m2m_user", CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK,
1290+
21, 0, 0),
1291+
GATE(CLK_GOUT_MFCMSCL_MCSC_CLK, "gout_mfcmscl_mcsc_clk",
1292+
"mout_mfcmscl_mcsc_user", CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK,
1293+
21, 0, 0),
1294+
GATE(CLK_GOUT_MFCMSCL_MFC_ACLK, "gout_mfcmscl_mfc_aclk",
1295+
"mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK,
1296+
21, 0, 0),
1297+
GATE(CLK_GOUT_MFCMSCL_PPMU_ACLK, "gout_mfcmscl_ppmu_aclk",
1298+
"mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK,
1299+
21, 0, 0),
1300+
GATE(CLK_GOUT_MFCMSCL_PPMU_PCLK, "gout_mfcmscl_ppmu_pclk",
1301+
"dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK,
1302+
21, 0, 0),
1303+
GATE(CLK_GOUT_MFCMSCL_SYSMMU_CLK, "gout_mfcmscl_sysmmu_clk",
1304+
"mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1,
1305+
21, 0, 0),
1306+
GATE(CLK_GOUT_MFCMSCL_SYSREG_PCLK, "gout_mfcmscl_sysreg_pclk",
1307+
"dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK,
1308+
21, 0, 0),
1309+
};
1310+
1311+
static const struct samsung_cmu_info mfcmscl_cmu_info __initconst = {
1312+
.mux_clks = mfcmscl_mux_clks,
1313+
.nr_mux_clks = ARRAY_SIZE(mfcmscl_mux_clks),
1314+
.div_clks = mfcmscl_div_clks,
1315+
.nr_div_clks = ARRAY_SIZE(mfcmscl_div_clks),
1316+
.gate_clks = mfcmscl_gate_clks,
1317+
.nr_gate_clks = ARRAY_SIZE(mfcmscl_gate_clks),
1318+
.nr_clk_ids = MFCMSCL_NR_CLK,
1319+
.clk_regs = mfcmscl_clk_regs,
1320+
.nr_clk_regs = ARRAY_SIZE(mfcmscl_clk_regs),
1321+
.clk_name = "dout_mfcmscl_mfc",
1322+
};
1323+
11511324
/* ---- CMU_PERI ------------------------------------------------------------ */
11521325

11531326
/* Register Offset definitions for CMU_PERI (0x10030000) */
@@ -1533,6 +1706,9 @@ static const struct of_device_id exynos850_cmu_of_match[] = {
15331706
}, {
15341707
.compatible = "samsung,exynos850-cmu-is",
15351708
.data = &is_cmu_info,
1709+
}, {
1710+
.compatible = "samsung,exynos850-cmu-mfcmscl",
1711+
.data = &mfcmscl_cmu_info,
15361712
}, {
15371713
.compatible = "samsung,exynos850-cmu-core",
15381714
.data = &core_cmu_info,

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