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perf vendor events: Update events for snowridgex
Update the events to v1.20, update events for snowridgex by the latest event converter tools. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/download_and_gen.py to download and generate the latest events and metrics. Manually copy the snowridgex files into perf. Signed-off-by: Xing Zhengjun <[email protected]> Tested-by: Ian Rogers <[email protected]> Cc: Alexander Shishkin <[email protected]> Cc: Andi Kleen <[email protected]> Cc: Ian Rogers <[email protected]> Cc: Ingo Molnar <[email protected]> Cc: Jiri Olsa <[email protected]> Cc: Kan Liang <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
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‎tools/perf/pmu-events/arch/x86/snowridgex/uncore-other.json‎

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@@ -132,23 +132,22 @@
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"Unit": "CHA"
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},
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{
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"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.ia_miss",
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"BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC",
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"Counter": "0,1,2,3",
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"CounterType": "PGMABLE",
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"EventCode": "0x35",
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"EventName": "LLC_MISSES.UNCACHEABLE",
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"Filter": "config1=0x40e33",
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"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
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"PerPkg": "1",
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"UMask": "0xC001FE01",
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"UMaskExt": "0xC001FE",
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"Unit": "CHA"
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},
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{
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"BriefDescription": "LLC misses - Uncacheable reads (from cpu) ",
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"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.ia_miss",
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"Counter": "0,1,2,3",
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"CounterType": "PGMABLE",
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"EventCode": "0x35",
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"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
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"EventName": "LLC_MISSES.UNCACHEABLE",
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"Filter": "config1=0x40e33",
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"PerPkg": "1",
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"UMask": "0xC001FE01",
@@ -167,18 +166,6 @@
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"UMaskExt": "0xC001FE",
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"Unit": "CHA"
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},
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{
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"BriefDescription": "MMIO reads",
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"Counter": "0,1,2,3",
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"CounterType": "PGMABLE",
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"EventCode": "0x35",
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"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
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"Filter": "config1=0x40040e33",
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"PerPkg": "1",
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"UMask": "0xC001FE01",
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"UMaskExt": "0xC001FE",
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"Unit": "CHA"
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},
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{
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"BriefDescription": "MMIO writes. Derived from unc_cha_tor_inserts.ia_miss",
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"Counter": "0,1,2,3",
@@ -191,18 +178,6 @@
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"UMaskExt": "0xC001FE",
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"Unit": "CHA"
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},
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{
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"BriefDescription": "MMIO writes",
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"Counter": "0,1,2,3",
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"CounterType": "PGMABLE",
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"EventCode": "0x35",
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"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
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"Filter": "config1=0x40041e33",
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"PerPkg": "1",
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"UMask": "0xC001FE01",
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"UMaskExt": "0xC001FE",
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"Unit": "CHA"
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},
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{
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"BriefDescription": "Streaming stores (full cache line). Derived from unc_cha_tor_inserts.ia_miss",
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"Counter": "0,1,2,3",
@@ -216,19 +191,6 @@
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"UMaskExt": "0xC001FE",
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"Unit": "CHA"
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},
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{
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"BriefDescription": "Streaming stores (full cache line)",
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"Counter": "0,1,2,3",
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"CounterType": "PGMABLE",
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"EventCode": "0x35",
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"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
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"Filter": "config1=0x41833",
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"PerPkg": "1",
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"ScaleUnit": "64Bytes",
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"UMask": "0xC001FE01",
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"UMaskExt": "0xC001FE",
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"Unit": "CHA"
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},
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{
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"BriefDescription": "Streaming stores (partial cache line). Derived from unc_cha_tor_inserts.ia_miss",
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"Counter": "0,1,2,3",
@@ -242,19 +204,6 @@
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"UMaskExt": "0xC001FE",
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"Unit": "CHA"
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},
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{
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"BriefDescription": "Streaming stores (partial cache line)",
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"Counter": "0,1,2,3",
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"CounterType": "PGMABLE",
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"EventCode": "0x35",
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"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
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"Filter": "config1=0x41a33",
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"PerPkg": "1",
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"ScaleUnit": "64Bytes",
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"UMask": "0xC001FE01",
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"UMaskExt": "0xC001FE",
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"Unit": "CHA"
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},
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{
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"BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC",
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"Counter": "0,1,2,3",
@@ -829,31 +778,12 @@
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"Unit": "IIO"
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},
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{
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"BriefDescription": "PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0",
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"Counter": "0,1",
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"CounterType": "PGMABLE",
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"EventCode": "0x83",
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"EventName": "LLC_MISSES.PCIE_WRITE",
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"FCMask": "0x07",
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"Filter": "ch_mask=0x1f",
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"MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
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"MetricName": "LLC_MISSES.PCIE_WRITE",
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"PerPkg": "1",
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"PortMask": "0x01",
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"ScaleUnit": "4Bytes",
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"UMask": "0x01",
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"Unit": "IIO"
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},
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{
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"BriefDescription": "PCI Express bandwidth writing at IIO",
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"BriefDescription": "PCI Express bandwidth writing at IIO, part 0",
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"Counter": "0,1",
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"CounterType": "PGMABLE",
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"EventCode": "0x83",
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"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
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"FCMask": "0x07",
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"Filter": "ch_mask=0x1f",
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"MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
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"MetricName": "LLC_MISSES.PCIE_WRITE",
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"PerPkg": "1",
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"PortMask": "0x01",
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"ScaleUnit": "4Bytes",
@@ -900,31 +830,28 @@
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"Unit": "IIO"
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},
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{
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"BriefDescription": "PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0",
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"BriefDescription": "PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0",
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"Counter": "0,1",
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"CounterType": "PGMABLE",
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"EventCode": "0x83",
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"EventName": "LLC_MISSES.PCIE_READ",
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"EventName": "LLC_MISSES.PCIE_WRITE",
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"FCMask": "0x07",
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"Filter": "ch_mask=0x1f",
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"MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
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"MetricName": "LLC_MISSES.PCIE_READ",
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"MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
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"MetricName": "LLC_MISSES.PCIE_WRITE",
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"PerPkg": "1",
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"PortMask": "0x01",
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"ScaleUnit": "4Bytes",
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"UMask": "0x04",
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"UMask": "0x01",
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"Unit": "IIO"
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},
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{
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"BriefDescription": "PCI Express bandwidth reading at IIO",
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"BriefDescription": "PCI Express bandwidth reading at IIO, part 0",
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"Counter": "0,1",
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"CounterType": "PGMABLE",
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"EventCode": "0x83",
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"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
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"FCMask": "0x07",
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"Filter": "ch_mask=0x1f",
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"MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
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"MetricName": "LLC_MISSES.PCIE_READ",
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"PerPkg": "1",
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"PortMask": "0x01",
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"ScaleUnit": "4Bytes",
@@ -970,6 +897,22 @@
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"UMask": "0x04",
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"Unit": "IIO"
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},
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{
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"BriefDescription": "PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0",
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"Counter": "0,1",
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"CounterType": "PGMABLE",
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"EventCode": "0x83",
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"EventName": "LLC_MISSES.PCIE_READ",
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"FCMask": "0x07",
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"Filter": "ch_mask=0x1f",
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"MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
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"MetricName": "LLC_MISSES.PCIE_READ",
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"PerPkg": "1",
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"PortMask": "0x01",
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"ScaleUnit": "4Bytes",
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"UMask": "0x04",
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"Unit": "IIO"
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},
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{
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"BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
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"Counter": "0,1",

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