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clk: mediatek: add driver for MT8365 SoC
Add clock drivers for MT8365 SoC. Signed-off-by: Fabien Parent <[email protected]> Signed-off-by: Markus Schneider-Pargmann <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reported-by: kernel test robot <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
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‎drivers/clk/mediatek/Kconfig‎

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Original file line numberDiff line numberDiff line change
@@ -645,6 +645,56 @@ config COMMON_CLK_MT8195
645645
help
646646
This driver supports MediaTek MT8195 clocks.
647647

648+
config COMMON_CLK_MT8365
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tristate "Clock driver for MediaTek MT8365"
650+
depends on ARCH_MEDIATEK || COMPILE_TEST
651+
select COMMON_CLK_MEDIATEK
652+
default ARCH_MEDIATEK && ARM64
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help
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This driver supports MediaTek MT8365 basic clocks.
655+
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config COMMON_CLK_MT8365_APU
657+
tristate "Clock driver for MediaTek MT8365 apu"
658+
depends on COMMON_CLK_MT8365
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default COMMON_CLK_MT8365
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help
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This driver supports MediaTek MT8365 apu clocks.
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config COMMON_CLK_MT8365_CAM
664+
tristate "Clock driver for MediaTek MT8365 cam"
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depends on COMMON_CLK_MT8365
666+
default COMMON_CLK_MT8365
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help
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This driver supports MediaTek MT8365 cam clocks.
669+
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config COMMON_CLK_MT8365_MFG
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tristate "Clock driver for MediaTek MT8365 mfg"
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depends on COMMON_CLK_MT8365
673+
default COMMON_CLK_MT8365
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help
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This driver supports MediaTek MT8365 mfg clocks.
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config COMMON_CLK_MT8365_MMSYS
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tristate "Clock driver for MediaTek MT8365 mmsys"
679+
depends on COMMON_CLK_MT8365
680+
default COMMON_CLK_MT8365
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help
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This driver supports MediaTek MT8365 mmsys clocks.
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config COMMON_CLK_MT8365_VDEC
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tristate "Clock driver for MediaTek MT8365 vdec"
686+
depends on COMMON_CLK_MT8365
687+
default COMMON_CLK_MT8365
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help
689+
This driver supports MediaTek MT8365 vdec clocks.
690+
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config COMMON_CLK_MT8365_VENC
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tristate "Clock driver for MediaTek MT8365 venc"
693+
depends on COMMON_CLK_MT8365
694+
default COMMON_CLK_MT8365
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help
696+
This driver supports MediaTek MT8365 venc clocks.
697+
648698
config COMMON_CLK_MT8516
649699
bool "Clock driver for MediaTek MT8516"
650700
depends on ARCH_MEDIATEK || COMPILE_TEST

‎drivers/clk/mediatek/Makefile‎

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Original file line numberDiff line numberDiff line change
@@ -103,5 +103,12 @@ obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195-apmixedsys.o clk-mt8195-topckgen.o
103103
clk-mt8195-venc.o clk-mt8195-vpp0.o clk-mt8195-vpp1.o \
104104
clk-mt8195-wpe.o clk-mt8195-imp_iic_wrap.o \
105105
clk-mt8195-apusys_pll.o
106+
obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365.o
107+
obj-$(CONFIG_COMMON_CLK_MT8365_APU) += clk-mt8365-apu.o
108+
obj-$(CONFIG_COMMON_CLK_MT8365_CAM) += clk-mt8365-cam.o
109+
obj-$(CONFIG_COMMON_CLK_MT8365_MFG) += clk-mt8365-mfg.o
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obj-$(CONFIG_COMMON_CLK_MT8365_MMSYS) += clk-mt8365-mm.o
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obj-$(CONFIG_COMMON_CLK_MT8365_VDEC) += clk-mt8365-vdec.o
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obj-$(CONFIG_COMMON_CLK_MT8365_VENC) += clk-mt8365-venc.o
106113
obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
107114
obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o

‎drivers/clk/mediatek/clk-mt8365-apu.c‎

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@@ -0,0 +1,55 @@
1+
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2022 MediaTek Inc.
4+
*/
5+
6+
#include <dt-bindings/clock/mediatek,mt8365-clk.h>
7+
#include <linux/clk-provider.h>
8+
#include <linux/platform_device.h>
9+
10+
#include "clk-gate.h"
11+
#include "clk-mtk.h"
12+
13+
static const struct mtk_gate_regs apu_cg_regs = {
14+
.set_ofs = 0x4,
15+
.clr_ofs = 0x8,
16+
.sta_ofs = 0x0,
17+
};
18+
19+
#define GATE_APU(_id, _name, _parent, _shift) \
20+
GATE_MTK(_id, _name, _parent, &apu_cg_regs, _shift, \
21+
&mtk_clk_gate_ops_setclr)
22+
23+
static const struct mtk_gate apu_clks[] = {
24+
GATE_APU(CLK_APU_AHB, "apu_ahb", "ifr_apu_axi", 5),
25+
GATE_APU(CLK_APU_EDMA, "apu_edma", "apu_sel", 4),
26+
GATE_APU(CLK_APU_IF_CK, "apu_if_ck", "apu_if_sel", 3),
27+
GATE_APU(CLK_APU_JTAG, "apu_jtag", "clk26m", 2),
28+
GATE_APU(CLK_APU_AXI, "apu_axi", "apu_sel", 1),
29+
GATE_APU(CLK_APU_IPU_CK, "apu_ck", "apu_sel", 0),
30+
};
31+
32+
static const struct mtk_clk_desc apu_desc = {
33+
.clks = apu_clks,
34+
.num_clks = ARRAY_SIZE(apu_clks),
35+
};
36+
37+
static const struct of_device_id of_match_clk_mt8365_apu[] = {
38+
{
39+
.compatible = "mediatek,mt8365-apu",
40+
.data = &apu_desc,
41+
}, {
42+
/* sentinel */
43+
}
44+
};
45+
46+
static struct platform_driver clk_mt8365_apu_drv = {
47+
.probe = mtk_clk_simple_probe,
48+
.remove = mtk_clk_simple_remove,
49+
.driver = {
50+
.name = "clk-mt8365-apu",
51+
.of_match_table = of_match_clk_mt8365_apu,
52+
},
53+
};
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builtin_platform_driver(clk_mt8365_apu_drv);
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MODULE_LICENSE("GPL");

‎drivers/clk/mediatek/clk-mt8365-cam.c‎

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@@ -0,0 +1,57 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2022 MediaTek Inc.
4+
*/
5+
6+
#include <dt-bindings/clock/mediatek,mt8365-clk.h>
7+
#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
9+
10+
#include "clk-gate.h"
11+
#include "clk-mtk.h"
12+
13+
static const struct mtk_gate_regs cam_cg_regs = {
14+
.set_ofs = 0x4,
15+
.clr_ofs = 0x8,
16+
.sta_ofs = 0x0,
17+
};
18+
19+
#define GATE_CAM(_id, _name, _parent, _shift) \
20+
GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, \
21+
&mtk_clk_gate_ops_setclr)
22+
23+
static const struct mtk_gate cam_clks[] = {
24+
GATE_CAM(CLK_CAM_LARB2, "cam_larb2", "mm_sel", 0),
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GATE_CAM(CLK_CAM, "cam", "mm_sel", 6),
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GATE_CAM(CLK_CAMTG, "camtg", "mm_sel", 7),
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GATE_CAM(CLK_CAM_SENIF, "cam_senif", "mm_sel", 8),
28+
GATE_CAM(CLK_CAMSV0, "camsv0", "mm_sel", 9),
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GATE_CAM(CLK_CAMSV1, "camsv1", "mm_sel", 10),
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GATE_CAM(CLK_CAM_FDVT, "cam_fdvt", "mm_sel", 11),
31+
GATE_CAM(CLK_CAM_WPE, "cam_wpe", "mm_sel", 12),
32+
};
33+
34+
static const struct mtk_clk_desc cam_desc = {
35+
.clks = cam_clks,
36+
.num_clks = ARRAY_SIZE(cam_clks),
37+
};
38+
39+
static const struct of_device_id of_match_clk_mt8365_cam[] = {
40+
{
41+
.compatible = "mediatek,mt8365-imgsys",
42+
.data = &cam_desc,
43+
}, {
44+
/* sentinel */
45+
}
46+
};
47+
48+
static struct platform_driver clk_mt8365_cam_drv = {
49+
.probe = mtk_clk_simple_probe,
50+
.remove = mtk_clk_simple_remove,
51+
.driver = {
52+
.name = "clk-mt8365-cam",
53+
.of_match_table = of_match_clk_mt8365_cam,
54+
},
55+
};
56+
builtin_platform_driver(clk_mt8365_cam_drv);
57+
MODULE_LICENSE("GPL");

‎drivers/clk/mediatek/clk-mt8365-mfg.c‎

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// SPDX-License-Identifier: GPL-2.0
2+
/*
3+
* Copyright (C) 2022 MediaTek Inc.
4+
*/
5+
6+
#include <dt-bindings/clock/mediatek,mt8365-clk.h>
7+
#include <linux/clk-provider.h>
8+
#include <linux/platform_device.h>
9+
10+
#include "clk-gate.h"
11+
#include "clk-mtk.h"
12+
13+
static const struct mtk_gate_regs mfg0_cg_regs = {
14+
.set_ofs = 0x4,
15+
.clr_ofs = 0x8,
16+
.sta_ofs = 0x0,
17+
};
18+
19+
static const struct mtk_gate_regs mfg1_cg_regs = {
20+
.set_ofs = 0x280,
21+
.clr_ofs = 0x280,
22+
.sta_ofs = 0x280,
23+
};
24+
25+
#define GATE_MFG0(_id, _name, _parent, _shift) \
26+
GATE_MTK(_id, _name, _parent, &mfg0_cg_regs, _shift, \
27+
&mtk_clk_gate_ops_setclr)
28+
29+
#define GATE_MFG1(_id, _name, _parent, _shift) \
30+
GATE_MTK(_id, _name, _parent, &mfg1_cg_regs, _shift, \
31+
&mtk_clk_gate_ops_no_setclr)
32+
33+
static const struct mtk_gate mfg_clks[] = {
34+
/* MFG0 */
35+
GATE_MFG0(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0),
36+
/* MFG1 */
37+
GATE_MFG1(CLK_MFG_MBIST_DIAG, "mfg_mbist_diag", "mbist_diag_sel", 24),
38+
};
39+
40+
static const struct mtk_clk_desc mfg_desc = {
41+
.clks = mfg_clks,
42+
.num_clks = ARRAY_SIZE(mfg_clks),
43+
};
44+
45+
static const struct of_device_id of_match_clk_mt8365_mfg[] = {
46+
{
47+
.compatible = "mediatek,mt8365-mfgcfg",
48+
.data = &mfg_desc,
49+
}, {
50+
/* sentinel */
51+
}
52+
};
53+
54+
static struct platform_driver clk_mt8365_mfg_drv = {
55+
.probe = mtk_clk_simple_probe,
56+
.remove = mtk_clk_simple_remove,
57+
.driver = {
58+
.name = "clk-mt8365-mfg",
59+
.of_match_table = of_match_clk_mt8365_mfg,
60+
},
61+
};
62+
builtin_platform_driver(clk_mt8365_mfg_drv);
63+
MODULE_LICENSE("GPL");

‎drivers/clk/mediatek/clk-mt8365-mm.c‎

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@@ -0,0 +1,112 @@
1+
// SPDX-License-Identifier: GPL-2.0
2+
/*
3+
* Copyright (C) 2022 MediaTek Inc.
4+
* Copyright (c) 2022 BayLibre, SAS
5+
*/
6+
7+
#include <dt-bindings/clock/mediatek,mt8365-clk.h>
8+
#include <linux/clk-provider.h>
9+
#include <linux/platform_device.h>
10+
11+
#include "clk-gate.h"
12+
#include "clk-mtk.h"
13+
14+
static const struct mtk_gate_regs mm0_cg_regs = {
15+
.set_ofs = 0x104,
16+
.clr_ofs = 0x108,
17+
.sta_ofs = 0x100,
18+
};
19+
20+
static const struct mtk_gate_regs mm1_cg_regs = {
21+
.set_ofs = 0x114,
22+
.clr_ofs = 0x118,
23+
.sta_ofs = 0x110,
24+
};
25+
26+
#define GATE_MM0(_id, _name, _parent, _shift) \
27+
GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, \
28+
&mtk_clk_gate_ops_setclr)
29+
30+
#define GATE_MM1(_id, _name, _parent, _shift) \
31+
GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, \
32+
&mtk_clk_gate_ops_setclr)
33+
34+
static const struct mtk_gate mm_clks[] = {
35+
/* MM0 */
36+
GATE_MM0(CLK_MM_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 0),
37+
GATE_MM0(CLK_MM_MM_MDP_CCORR0, "mm_mdp_ccorr0", "mm_sel", 1),
38+
GATE_MM0(CLK_MM_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 2),
39+
GATE_MM0(CLK_MM_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 3),
40+
GATE_MM0(CLK_MM_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 4),
41+
GATE_MM0(CLK_MM_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 5),
42+
GATE_MM0(CLK_MM_MM_MDP_WDMA0, "mm_mdp_wdma0", "mm_sel", 6),
43+
GATE_MM0(CLK_MM_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 7),
44+
GATE_MM0(CLK_MM_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_sel", 8),
45+
GATE_MM0(CLK_MM_MM_DISP_RSZ0, "mm_disp_rsz0", "mm_sel", 9),
46+
GATE_MM0(CLK_MM_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 10),
47+
GATE_MM0(CLK_MM_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 11),
48+
GATE_MM0(CLK_MM_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 12),
49+
GATE_MM0(CLK_MM_MM_DISP_CCORR0, "mm_disp_ccorr0", "mm_sel", 13),
50+
GATE_MM0(CLK_MM_MM_DISP_AAL0, "mm_disp_aal0", "mm_sel", 14),
51+
GATE_MM0(CLK_MM_MM_DISP_GAMMA0, "mm_disp_gamma0", "mm_sel", 15),
52+
GATE_MM0(CLK_MM_MM_DISP_DITHER0, "mm_disp_dither0", "mm_sel", 16),
53+
GATE_MM0(CLK_MM_MM_DSI0, "mm_dsi0", "mm_sel", 17),
54+
GATE_MM0(CLK_MM_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 18),
55+
GATE_MM0(CLK_MM_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 19),
56+
GATE_MM0(CLK_MM_DPI0_DPI0, "mm_dpi0_dpi0", "vpll_dpix", 20),
57+
GATE_MM0(CLK_MM_MM_FAKE, "mm_fake", "mm_sel", 21),
58+
GATE_MM0(CLK_MM_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 22),
59+
GATE_MM0(CLK_MM_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 23),
60+
GATE_MM0(CLK_MM_MM_SMI_COMM0, "mm_smi_comm0", "mm_sel", 24),
61+
GATE_MM0(CLK_MM_MM_SMI_COMM1, "mm_smi_comm1", "mm_sel", 25),
62+
GATE_MM0(CLK_MM_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 26),
63+
GATE_MM0(CLK_MM_MM_SMI_IMG, "mm_smi_img", "mm_sel", 27),
64+
GATE_MM0(CLK_MM_MM_SMI_CAM, "mm_smi_cam", "mm_sel", 28),
65+
GATE_MM0(CLK_MM_IMG_IMG_DL_RELAY, "mm_dl_relay", "mm_sel", 29),
66+
GATE_MM0(CLK_MM_IMG_IMG_DL_ASYNC_TOP, "mm_dl_async_top", "mm_sel", 30),
67+
GATE_MM0(CLK_MM_DSI0_DIG_DSI, "mm_dsi0_dig_dsi", "dsi0_lntc_dsick", 31),
68+
/* MM1 */
69+
GATE_MM1(CLK_MM_26M_HRTWT, "mm_f26m_hrtwt", "clk26m", 0),
70+
GATE_MM1(CLK_MM_MM_DPI0, "mm_dpi0", "mm_sel", 1),
71+
GATE_MM1(CLK_MM_LVDSTX_PXL, "mm_flvdstx_pxl", "vpll_dpix", 2),
72+
GATE_MM1(CLK_MM_LVDSTX_CTS, "mm_flvdstx_cts", "lvdstx_dig_cts", 3),
73+
};
74+
75+
static int clk_mt8365_mm_probe(struct platform_device *pdev)
76+
{
77+
struct device *dev = &pdev->dev;
78+
struct device_node *node = dev->parent->of_node;
79+
struct clk_hw_onecell_data *clk_data;
80+
int ret;
81+
82+
clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
83+
84+
ret = mtk_clk_register_gates_with_dev(node, mm_clks,
85+
ARRAY_SIZE(mm_clks), clk_data,
86+
dev);
87+
if (ret)
88+
goto err_free_clk_data;
89+
90+
ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
91+
if (ret)
92+
goto err_unregister_gates;
93+
94+
return 0;
95+
96+
err_unregister_gates:
97+
mtk_clk_unregister_gates(mm_clks, ARRAY_SIZE(mm_clks), clk_data);
98+
99+
err_free_clk_data:
100+
mtk_free_clk_data(clk_data);
101+
102+
return ret;
103+
}
104+
105+
static struct platform_driver clk_mt8365_mm_drv = {
106+
.probe = clk_mt8365_mm_probe,
107+
.driver = {
108+
.name = "clk-mt8365-mm",
109+
},
110+
};
111+
builtin_platform_driver(clk_mt8365_mm_drv);
112+
MODULE_LICENSE("GPL");

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