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Original file line number Diff line number Diff line change 1+ # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2+ %YAML 1.2
3+ ---
4+ $id : http://devicetree.org/schemas/clock/rockchip,rk3128-cru.yaml#
5+ $schema : http://devicetree.org/meta-schemas/core.yaml#
6+
7+ title : Rockchip RK3126/RK3128 Clock and Reset Unit (CRU)
8+
9+ maintainers :
10+ -
Elaine Zhang <[email protected] > 11+ -
Heiko Stuebner <[email protected] > 12+
13+ description : |
14+ The RK3126/RK3128 clock controller generates and supplies clock to various
15+ controllers within the SoC and also implements a reset controller for SoC
16+ peripherals.
17+ Each clock is assigned an identifier and client nodes can use this identifier
18+ to specify the clock which they consume. All available clocks are defined as
19+ preprocessor macros in the dt-bindings/clock/rk3128-cru.h headers and can be
20+ used in device tree sources. Similar macros exist for the reset sources in
21+ these files.
22+
23+ properties :
24+ compatible :
25+ enum :
26+ - rockchip,rk3126-cru
27+ - rockchip,rk3128-cru
28+
29+ reg :
30+ maxItems : 1
31+
32+ " #clock-cells " :
33+ const : 1
34+
35+ " #reset-cells " :
36+ const : 1
37+
38+ clocks :
39+ minItems : 1
40+ maxItems : 3
41+
42+ clock-names :
43+ minItems : 1
44+ items :
45+ - const : xin24m
46+ - enum :
47+ - ext_i2s
48+ - gmac_clkin
49+ - enum :
50+ - ext_i2s
51+ - gmac_clkin
52+
53+ rockchip,grf :
54+ $ref : /schemas/types.yaml#/definitions/phandle
55+ description :
56+ Phandle to the syscon managing the "general register files" (GRF),
57+ if missing pll rates are not changeable, due to the missing pll
58+ lock status.
59+
60+ required :
61+ - compatible
62+ - reg
63+ - " #clock-cells"
64+ - " #reset-cells"
65+
66+ additionalProperties : false
67+
68+ examples :
69+ - |
70+ cru: clock-controller@20000000 {
71+ compatible = "rockchip,rk3128-cru";
72+ reg = <0x20000000 0x1000>;
73+ rockchip,grf = <&grf>;
74+ #clock-cells = <1>;
75+ #reset-cells = <1>;
76+ };
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