@@ -51,6 +51,7 @@ enum imx6_pcie_variants {
5151 IMX7D ,
5252 IMX8MQ ,
5353 IMX8MM ,
54+ IMX8MP ,
5455};
5556
5657#define IMX6_PCIE_FLAG_IMX6_PHY BIT(0)
@@ -61,6 +62,7 @@ struct imx6_pcie_drvdata {
6162 enum imx6_pcie_variants variant ;
6263 u32 flags ;
6364 int dbi_length ;
65+ const char * gpr ;
6466};
6567
6668struct imx6_pcie {
@@ -150,7 +152,8 @@ struct imx6_pcie {
150152static unsigned int imx6_pcie_grp_offset (const struct imx6_pcie * imx6_pcie )
151153{
152154 WARN_ON (imx6_pcie -> drvdata -> variant != IMX8MQ &&
153- imx6_pcie -> drvdata -> variant != IMX8MM );
155+ imx6_pcie -> drvdata -> variant != IMX8MM &&
156+ imx6_pcie -> drvdata -> variant != IMX8MP );
154157 return imx6_pcie -> controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14 ;
155158}
156159
@@ -301,6 +304,7 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
301304{
302305 switch (imx6_pcie -> drvdata -> variant ) {
303306 case IMX8MM :
307+ case IMX8MP :
304308 /*
305309 * The PHY initialization had been done in the PHY
306310 * driver, break here directly.
@@ -558,6 +562,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
558562 break ;
559563 case IMX8MM :
560564 case IMX8MQ :
565+ case IMX8MP :
561566 ret = clk_prepare_enable (imx6_pcie -> pcie_aux );
562567 if (ret ) {
563568 dev_err (dev , "unable to enable pcie_aux clock\n" );
@@ -602,6 +607,7 @@ static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie)
602607 break ;
603608 case IMX8MM :
604609 case IMX8MQ :
610+ case IMX8MP :
605611 clk_disable_unprepare (imx6_pcie -> pcie_aux );
606612 break ;
607613 default :
@@ -669,6 +675,7 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
669675 reset_control_assert (imx6_pcie -> pciephy_reset );
670676 fallthrough ;
671677 case IMX8MM :
678+ case IMX8MP :
672679 reset_control_assert (imx6_pcie -> apps_reset );
673680 break ;
674681 case IMX6SX :
@@ -744,6 +751,7 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
744751 break ;
745752 case IMX6Q : /* Nothing to do */
746753 case IMX8MM :
754+ case IMX8MP :
747755 break ;
748756 }
749757
@@ -793,6 +801,7 @@ static void imx6_pcie_ltssm_enable(struct device *dev)
793801 case IMX7D :
794802 case IMX8MQ :
795803 case IMX8MM :
804+ case IMX8MP :
796805 reset_control_deassert (imx6_pcie -> apps_reset );
797806 break ;
798807 }
@@ -812,6 +821,7 @@ static void imx6_pcie_ltssm_disable(struct device *dev)
812821 case IMX7D :
813822 case IMX8MQ :
814823 case IMX8MM :
824+ case IMX8MP :
815825 reset_control_assert (imx6_pcie -> apps_reset );
816826 break ;
817827 }
@@ -935,7 +945,7 @@ static int imx6_pcie_host_init(struct dw_pcie_rp *pp)
935945 }
936946
937947 if (imx6_pcie -> phy ) {
938- ret = phy_power_on (imx6_pcie -> phy );
948+ ret = phy_init (imx6_pcie -> phy );
939949 if (ret ) {
940950 dev_err (dev , "pcie PHY power up failed\n" );
941951 goto err_clk_disable ;
@@ -949,7 +959,7 @@ static int imx6_pcie_host_init(struct dw_pcie_rp *pp)
949959 }
950960
951961 if (imx6_pcie -> phy ) {
952- ret = phy_init (imx6_pcie -> phy );
962+ ret = phy_power_on (imx6_pcie -> phy );
953963 if (ret ) {
954964 dev_err (dev , "waiting for PHY ready timeout!\n" );
955965 goto err_phy_off ;
@@ -961,7 +971,7 @@ static int imx6_pcie_host_init(struct dw_pcie_rp *pp)
961971
962972err_phy_off :
963973 if (imx6_pcie -> phy )
964- phy_power_off (imx6_pcie -> phy );
974+ phy_exit (imx6_pcie -> phy );
965975err_clk_disable :
966976 imx6_pcie_clk_disable (imx6_pcie );
967977err_reg_disable :
@@ -1179,6 +1189,7 @@ static int imx6_pcie_probe(struct platform_device *pdev)
11791189 }
11801190 break ;
11811191 case IMX8MM :
1192+ case IMX8MP :
11821193 imx6_pcie -> pcie_aux = devm_clk_get (dev , "pcie_aux" );
11831194 if (IS_ERR (imx6_pcie -> pcie_aux ))
11841195 return dev_err_probe (dev , PTR_ERR (imx6_pcie -> pcie_aux ),
@@ -1216,7 +1227,7 @@ static int imx6_pcie_probe(struct platform_device *pdev)
12161227
12171228 /* Grab GPR config register range */
12181229 imx6_pcie -> iomuxc_gpr =
1219- syscon_regmap_lookup_by_compatible ("fsl,imx6q-iomuxc- gpr" );
1230+ syscon_regmap_lookup_by_compatible (imx6_pcie -> drvdata -> gpr );
12201231 if (IS_ERR (imx6_pcie -> iomuxc_gpr )) {
12211232 dev_err (dev , "unable to find iomuxc registers\n" );
12221233 return PTR_ERR (imx6_pcie -> iomuxc_gpr );
@@ -1295,30 +1306,41 @@ static const struct imx6_pcie_drvdata drvdata[] = {
12951306 .flags = IMX6_PCIE_FLAG_IMX6_PHY |
12961307 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE ,
12971308 .dbi_length = 0x200 ,
1309+ .gpr = "fsl,imx6q-iomuxc-gpr" ,
12981310 },
12991311 [IMX6SX ] = {
13001312 .variant = IMX6SX ,
13011313 .flags = IMX6_PCIE_FLAG_IMX6_PHY |
13021314 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE |
13031315 IMX6_PCIE_FLAG_SUPPORTS_SUSPEND ,
1316+ .gpr = "fsl,imx6q-iomuxc-gpr" ,
13041317 },
13051318 [IMX6QP ] = {
13061319 .variant = IMX6QP ,
13071320 .flags = IMX6_PCIE_FLAG_IMX6_PHY |
13081321 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE |
13091322 IMX6_PCIE_FLAG_SUPPORTS_SUSPEND ,
13101323 .dbi_length = 0x200 ,
1324+ .gpr = "fsl,imx6q-iomuxc-gpr" ,
13111325 },
13121326 [IMX7D ] = {
13131327 .variant = IMX7D ,
13141328 .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND ,
1329+ .gpr = "fsl,imx7d-iomuxc-gpr" ,
13151330 },
13161331 [IMX8MQ ] = {
13171332 .variant = IMX8MQ ,
1333+ .gpr = "fsl,imx8mq-iomuxc-gpr" ,
13181334 },
13191335 [IMX8MM ] = {
13201336 .variant = IMX8MM ,
13211337 .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND ,
1338+ .gpr = "fsl,imx8mm-iomuxc-gpr" ,
1339+ },
1340+ [IMX8MP ] = {
1341+ .variant = IMX8MP ,
1342+ .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND ,
1343+ .gpr = "fsl,imx8mp-iomuxc-gpr" ,
13221344 },
13231345};
13241346
@@ -1329,6 +1351,7 @@ static const struct of_device_id imx6_pcie_of_match[] = {
13291351 { .compatible = "fsl,imx7d-pcie" , .data = & drvdata [IMX7D ], },
13301352 { .compatible = "fsl,imx8mq-pcie" , .data = & drvdata [IMX8MQ ], },
13311353 { .compatible = "fsl,imx8mm-pcie" , .data = & drvdata [IMX8MM ], },
1354+ { .compatible = "fsl,imx8mp-pcie" , .data = & drvdata [IMX8MP ], },
13321355 {},
13331356};
13341357
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