[CPU] Switch CPUDefault pipeline to use IREE::CPU::LoweringConfigAttr. (iree-org#21515)

Signed-off-by: hanhanW <[email protected]>
Signed-off-by: keshavvinayak01 <[email protected]>

Author: hanhanW

compiler/src/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp

@@ -2130,7 +2130,9 @@ setDefaultGenericOpRootConfig(mlir::FunctionOpInterface entryPointFn,
   unsigned numLoops = genericOp.getNumLoops();
   if (numLoops == 0) {
     return setOpConfigAndEntryPointFnTranslation(
-        entryPointFn, genericOp, TileSizesListType{{}},
+        entryPointFn, genericOp,
+        IREE::CPU::LoweringConfigAttr::get(genericOp.getContext(),
+                                           SmallVector<NamedAttribute>()),
         DispatchLoweringPassPipeline::CPUDefault);
   }
 
@@ -2674,17 +2676,23 @@ static LogicalResult setRootConfig(mlir::FunctionOpInterface entryPointFn,
   assert(!getLoweringConfig(op) && "expected lowering_config is not set");
   SmallVector<int64_t> distTileSizes =
       getDefaultDistributedLevelTileSizes(op, DistributionHeuristicConfig{});
-  TileSizesListType tileSizes = {distTileSizes};
-  SmallVector<int64_t> vecTileSizes = distTileSizes;
 
   // Add an extra level of tiling.
   // TODO: Limit vector tile sizes for other TilingInterface ops.
+  SmallVector<int64_t> vecTileSizes = distTileSizes;
   if (auto linalgOp = dyn_cast<linalg::LinalgOp>(*op)) {
     limitVectorTileSizes(linalgOp, vecTileSizes);
   }
-  tileSizes.push_back(vecTileSizes);
+
+  LoweringConfigGenerator generator(op);
+  generator.setDistributionTileSizes(distTileSizes);
+  generator.setVectorTileSizes(vecTileSizes);
+  IREE::CPU::LoweringConfigAttr loweringConfig =
+      generator.generateCPULoweringConfig();
+  LDBG("Set lowering_config for tensor.pad op: " << loweringConfig);
   return setOpConfigAndEntryPointFnTranslation(
-      entryPointFn, op, tileSizes, DispatchLoweringPassPipeline::CPUDefault);
+      entryPointFn, op, loweringConfig,
+      DispatchLoweringPassPipeline::CPUDefault);
 }
 
 /// Redirects to methods that set the configuration based on operation type.

compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_x86_64_lowering_strategy.mlir

@@ -934,9 +934,12 @@ func.func @scalar() attributes {hal.executable.target = #executable_target_embed
   iree_tensor_ext.dispatch.tensor.store %4, %1, offsets = [], sizes = [], strides = [] : tensor<f32> -> !iree_tensor_ext.dispatch.tensor<writeonly:tensor<f32>>
   return
 }
+//  CHECK-DAG: #[[CONFIG:.+]] = #iree_cpu.lowering_config<distribution = []>
 //  CHECK-DAG: #[[TRANSLATION:.+]] = #iree_codegen.translation_info<pipeline = CPUDefault>
 //      CHECK: func.func @scalar()
 // CHECK-SAME:     translation_info = #[[TRANSLATION]]
+//      CHECK:   linalg.generic
+// CHECK-SAME:     lowering_config = #config
 
 // -----
 
@@ -2014,7 +2017,7 @@ func.func @test_tiling_cpu_default(%arg0: tensor<256x256xi8>, %arg1: tensor<256x
     %0 = linalg.quantized_matmul ins(%arg0, %arg1, %arg2, %arg3 : tensor<256x256xi8>, tensor<256x256xi8>, i32, i32) outs(%arg4 : tensor<256x256xi32>) -> tensor<256x256xi32>
     return %0 : tensor<256x256xi32>
 }
-// CHECK-DAG:  #[[CONFIG0:.+]] = #iree_codegen.lowering_config<tile_sizes = {{\[}}[64, 64, 0], [4, 64, 0]]>
+// CHECK-DAG:  #[[CONFIG0:.+]] = #iree_cpu.lowering_config<distribution = [64, 64, 0], vector_common_parallel = [4, 64, 0], vector_reduction = [0, 0, 0]>
 // CHECK-DAG:  #[[TRANSLATION_INFO]] = #iree_codegen.translation_info<pipeline = CPUDefault>
 //      CHECK: func @test_tiling_cpu_default(
 // CHECK-SAME:     translation_info = #[[TRANSLATION_INFO]]