Integrate LLVM at 92c55a3 (iree-org#21429)

Integrate
llvm/llvm-project@92c55a3.

Local changes adapt to
llvm/llvm-project@03bd0f3,
plus a fix to a preexisting issue in `vmvx_materialize_encoding.mlir`
which for some reason was tolerated up until now.

No reverts or cherry-picks: dropped the former local revert since
llvm/llvm-project#149393 was landed.

---------

Signed-off-by: Benoit Jacob <[email protected]>
Signed-off-by: keshavvinayak01 <[email protected]>

Author: bjacob

compiler/src/iree/compiler/Codegen/Common/ConvertBf16ArithToF32.cpp

@@ -285,8 +285,8 @@ struct ConvertBf16ArithToF32Pass final
     // Some arithmetic operations exist in the vector dialect.
     target.addDynamicallyLegalOp<vector::FMAOp, vector::ReductionOp,
                                  vector::MultiDimReductionOp, vector::MaskOp,
-                                 vector::MatmulOp, vector::OuterProductOp,
-                                 vector::YieldOp>(checkOp);
+                                 vector::OuterProductOp, vector::YieldOp>(
+        checkOp);
 
     // Some ops are always legal.
     target.addLegalOp<arith::BitcastOp>();

compiler/src/iree/compiler/Codegen/Common/ConvertBf16ToUInt16Buffers.cpp

@@ -320,13 +320,12 @@ struct ConvertBf16ToUInt16BuffersPass final
           vector::GatherOp, vector::ScatterOp, vector::ExpandLoadOp,
           vector::CompressStoreOp, vector::ShapeCastOp, vector::ConstantMaskOp,
           vector::CreateMaskOp, vector::MaskOp, vector::TransposeOp,
-          vector::FlatTransposeOp, vector::SplatOp, vector::YieldOp>(
-          [&typeConverter](Operation *op) {
-            bool legal = typeConverter.isLegal(op);
-            LLVM_DEBUG(if (!legal) llvm::dbgs()
-                       << "Bf16Emulation: illegal op: " << *op << "\n");
-            return legal;
-          });
+          vector::SplatOp, vector::YieldOp>([&typeConverter](Operation *op) {
+        bool legal = typeConverter.isLegal(op);
+        LLVM_DEBUG(if (!legal) llvm::dbgs()
+                   << "Bf16Emulation: illegal op: " << *op << "\n");
+        return legal;
+      });
 
       RewritePatternSet patterns(ctx);
       populateIreeBf16EmulationPatterns(patterns, typeConverter);

compiler/src/iree/compiler/Codegen/Common/test/vmvx_materialize_encoding.mlir

@@ -97,15 +97,15 @@ func.func @matmul_lowering_i8i8i32_vmvx_ukernel() attributes {
 #encoding_lhs = #iree_encoding.encoding<operand_index = 0, op_type = matmul, element_types = [f32, f32, f32], user_indexing_maps = [#map2, #map3, #map4], iteration_sizes = [1, 3, 2]>
 #encoding_rhs = #iree_encoding.encoding<operand_index = 1, op_type = matmul, element_types = [f32, f32, f32], user_indexing_maps = [#map2, #map3, #map4], iteration_sizes = [1, 3, 2]>
 #encoding_result = #iree_encoding.encoding<operand_index = 2, op_type = matmul, element_types = [f32, f32, f32], user_indexing_maps = [#map2, #map3, #map4], iteration_sizes = [1, 3, 2]>
-func.func @fill_matmul(%arg0: index, %arg1: index, %arg2: index, %arg3: index, %arg4: index, %arg5: index, %arg6: index, %arg7: index) attributes {
+func.func @fill_matmul() attributes {
   hal.executable.target = #hal.executable.target<"vmvx", "vmvx-bytecode-fb", {iree.encoding.resolver = #iree_cpu.vmvx_encoding_resolver<>}>
 } {
   %c32_i64 = arith.constant 32 : i64
   %cst = arith.constant 0.000000e+00 : f32
   %c0 = arith.constant 0 : index
   %0 = hal.interface.binding.subspan layout(#pipeline_layout) binding(0) alignment(64) offset(%c0) flags(ReadOnly) : !iree_tensor_ext.dispatch.tensor<readonly:tensor<1x2xf32, #encoding_lhs>>
   %1 = hal.interface.binding.subspan layout(#pipeline_layout) binding(1) alignment(64) offset(%c0) flags(ReadOnly) : !iree_tensor_ext.dispatch.tensor<readonly:tensor<2x3xf32, #encoding_rhs>>
-  %2 = hal.interface.binding.subspan layout(#pipeline_layout) binding(2) alignment(64) offset(%c0) : !iree_tensor_ext.dispatch.tensor<writeonly:tensor<1x3xf32, #encoding_result>>{%arg4, %arg5}
+  %2 = hal.interface.binding.subspan layout(#pipeline_layout) binding(2) alignment(64) offset(%c0) : !iree_tensor_ext.dispatch.tensor<writeonly:tensor<1x3xf32, #encoding_result>>
   %3 = iree_tensor_ext.dispatch.tensor.load %0, offsets = [0, 0], sizes = [1, 2], strides = [1, 1] : !iree_tensor_ext.dispatch.tensor<readonly:tensor<1x2xf32, #encoding_lhs>> -> tensor<1x2xf32, #encoding_lhs>
   %4 = iree_tensor_ext.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2, 3], strides = [1, 1] : !iree_tensor_ext.dispatch.tensor<readonly:tensor<2x3xf32, #encoding_rhs>> -> tensor<2x3xf32, #encoding_rhs>
   %7 = tensor.empty() : tensor<1x3xf32, #encoding_result>

compiler/src/iree/compiler/Codegen/LLVMCPU/ConvertToLLVM.cpp

@@ -1054,7 +1054,6 @@ void ConvertToLLVMPass::runOnOperation() {
   // Some n-D vectors are generated by EmulateNarrowType pass, so we need to
   // unroll them to 1-D before converting to the LLVM dialect.
   vector::populateVectorBitCastLoweringPatterns(patterns);
-  populateVectorToLLVMMatrixConversionPatterns(typeConverter, patterns);
   vector::populateVectorRankReducingFMAPattern(patterns);
   vector::populateVectorInsertExtractStridedSliceTransforms(patterns);
   vector::populateVectorStepLoweringPatterns(patterns);