drm/rockchip: vop2: calculate dclk first when dsc enable

When the request pixelclk is under 600MHz, vop2 will
calculate dclk first. When  the dsc is enabled. vop2 will
calculate dsc clk first then dclk. the dclk rate get from
the first time calclulate dsc clk and second set dck may
be different, which will get wrong dsc clk when use the
latest dclk rate to recalculate it. So the dclk should
be calculated before dsc clk when dsc enable and pixelclk
is under 600MHz.

Signed-off-by: Zhang Yubing <[email protected]>
Change-Id: If6794a266dd624be2cd14ab1be0ee0c0db20b49a

Author: Zhang Yubing

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

@@ -5914,19 +5914,6 @@ static int vop2_calc_if_clk(struct drm_crtc *crtc, const struct vop2_connector_i
 	snprintf(clk_name, sizeof(clk_name), "dclk_out%d", vp->id);
 	dclk_out = vop2_clk_get(vop2, clk_name);
 
-	if (vcstate->dsc_enable) {
-		if ((vcstate->dsc_txp_clk_rate >= dclk_core_rate) &&
-		    (vcstate->dsc_txp_clk_rate >= if_pixclk->rate)) {
-			dsc_txp_clk_is_biggest = true;
-			if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) {
-				vop2_set_dsc_clk(crtc, 0);
-				vop2_set_dsc_clk(crtc, 1);
-			} else {
-				vop2_set_dsc_clk(crtc, dsc_id);
-			}
-		}
-	}
-
 	/*
 	 * HDMI use 1:1 dclk for rgb/yuv444, 1:2 for yuv420 when
 	 * pixclk <= 600
@@ -5946,6 +5933,19 @@ static int vop2_calc_if_clk(struct drm_crtc *crtc, const struct vop2_connector_i
 		}
 	}
 
+	if (vcstate->dsc_enable) {
+		if ((vcstate->dsc_txp_clk_rate >= dclk_core_rate) &&
+		    (vcstate->dsc_txp_clk_rate >= if_pixclk->rate)) {
+			dsc_txp_clk_is_biggest = true;
+			if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) {
+				vop2_set_dsc_clk(crtc, 0);
+				vop2_set_dsc_clk(crtc, 1);
+			} else {
+				vop2_set_dsc_clk(crtc, dsc_id);
+			}
+		}
+	}
+
 	if (dclk_core_rate > if_pixclk->rate) {
 		clk_set_rate(dclk_core->hw.clk, dclk_core_rate);
 		if (output_if_is_mipi(conn_id))