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torvaldstorvalds
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Merge tag 'hwmon-for-linus-v4.17-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging
Pull hwmon fixes from Guenter Roeck: "Two k10temp fixes: - fix race condition when accessing System Management Network registers - fix reading critical temperatures on F15h M60h and M70h Also add PCI ID's for the AMD Raven Ridge root bridge" * tag 'hwmon-for-linus-v4.17-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging: hwmon: (k10temp) Use API function to access System Management Network x86/amd_nb: Add support for Raven Ridge CPUs hwmon: (k10temp) Fix reading critical temperature register
2 parents 58ddfe6 + 3b03162 commit 3acf4e3

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3 files changed

+43
-16
lines changed

3 files changed

+43
-16
lines changed

‎arch/x86/kernel/amd_nb.c‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,8 +14,11 @@
1414
#include <asm/amd_nb.h>
1515

1616
#define PCI_DEVICE_ID_AMD_17H_ROOT 0x1450
17+
#define PCI_DEVICE_ID_AMD_17H_M10H_ROOT 0x15d0
1718
#define PCI_DEVICE_ID_AMD_17H_DF_F3 0x1463
1819
#define PCI_DEVICE_ID_AMD_17H_DF_F4 0x1464
20+
#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 0x15eb
21+
#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F4 0x15ec
1922

2023
/* Protect the PCI config register pairs used for SMN and DF indirect access. */
2124
static DEFINE_MUTEX(smn_mutex);
@@ -24,6 +27,7 @@ static u32 *flush_words;
2427

2528
static const struct pci_device_id amd_root_ids[] = {
2629
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_ROOT) },
30+
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_ROOT) },
2731
{}
2832
};
2933

@@ -39,6 +43,7 @@ const struct pci_device_id amd_nb_misc_ids[] = {
3943
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
4044
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
4145
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
46+
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
4247
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
4348
{}
4449
};
@@ -51,6 +56,7 @@ static const struct pci_device_id amd_nb_link_ids[] = {
5156
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
5257
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
5358
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F4) },
59+
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F4) },
5460
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F4) },
5561
{}
5662
};

‎drivers/hwmon/Kconfig‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -272,7 +272,7 @@ config SENSORS_K8TEMP
272272

273273
config SENSORS_K10TEMP
274274
tristate "AMD Family 10h+ temperature sensor"
275-
depends on X86 && PCI
275+
depends on X86 && PCI && AMD_NB
276276
help
277277
If you say yes here you get support for the temperature
278278
sensor(s) inside your CPU. Supported are later revisions of

‎drivers/hwmon/k10temp.c‎

Lines changed: 36 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,7 @@
2323
#include <linux/init.h>
2424
#include <linux/module.h>
2525
#include <linux/pci.h>
26+
#include <asm/amd_nb.h>
2627
#include <asm/processor.h>
2728

2829
MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
@@ -40,8 +41,8 @@ static DEFINE_MUTEX(nb_smu_ind_mutex);
4041
#define PCI_DEVICE_ID_AMD_17H_DF_F3 0x1463
4142
#endif
4243

43-
#ifndef PCI_DEVICE_ID_AMD_17H_RR_NB
44-
#define PCI_DEVICE_ID_AMD_17H_RR_NB 0x15d0
44+
#ifndef PCI_DEVICE_ID_AMD_17H_M10H_DF_F3
45+
#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 0x15eb
4546
#endif
4647

4748
/* CPUID function 0x80000001, ebx */
@@ -63,17 +64,20 @@ static DEFINE_MUTEX(nb_smu_ind_mutex);
6364
#define NB_CAP_HTC 0x00000400
6465

6566
/*
66-
* For F15h M60h, functionality of REG_REPORTED_TEMPERATURE
67-
* has been moved to D0F0xBC_xD820_0CA4 [Reported Temperature
68-
* Control]
67+
* For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL
68+
* and REG_REPORTED_TEMPERATURE have been moved to
69+
* D0F0xBC_xD820_0C64 [Hardware Temperature Control]
70+
* D0F0xBC_xD820_0CA4 [Reported Temperature Control]
6971
*/
72+
#define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64
7073
#define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4
7174

7275
/* F17h M01h Access througn SMN */
7376
#define F17H_M01H_REPORTED_TEMP_CTRL_OFFSET 0x00059800
7477

7578
struct k10temp_data {
7679
struct pci_dev *pdev;
80+
void (*read_htcreg)(struct pci_dev *pdev, u32 *regval);
7781
void (*read_tempreg)(struct pci_dev *pdev, u32 *regval);
7882
int temp_offset;
7983
u32 temp_adjust_mask;
@@ -98,6 +102,11 @@ static const struct tctl_offset tctl_offset_table[] = {
98102
{ 0x17, "AMD Ryzen Threadripper 1910", 10000 },
99103
};
100104

105+
static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval)
106+
{
107+
pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval);
108+
}
109+
101110
static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval)
102111
{
103112
pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);
@@ -114,6 +123,12 @@ static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn,
114123
mutex_unlock(&nb_smu_ind_mutex);
115124
}
116125

126+
static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval)
127+
{
128+
amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
129+
F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval);
130+
}
131+
117132
static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval)
118133
{
119134
amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
@@ -122,8 +137,8 @@ static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval)
122137

123138
static void read_tempreg_nb_f17(struct pci_dev *pdev, u32 *regval)
124139
{
125-
amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0x60,
126-
F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, regval);
140+
amd_smn_read(amd_pci_dev_to_node_id(pdev),
141+
F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, regval);
127142
}
128143

129144
static ssize_t temp1_input_show(struct device *dev,
@@ -160,8 +175,7 @@ static ssize_t show_temp_crit(struct device *dev,
160175
u32 regval;
161176
int value;
162177

163-
pci_read_config_dword(data->pdev,
164-
REG_HARDWARE_THERMAL_CONTROL, &regval);
178+
data->read_htcreg(data->pdev, &regval);
165179
value = ((regval >> 16) & 0x7f) * 500 + 52000;
166180
if (show_hyst)
167181
value -= ((regval >> 24) & 0xf) * 500;
@@ -181,13 +195,18 @@ static umode_t k10temp_is_visible(struct kobject *kobj,
181195
struct pci_dev *pdev = data->pdev;
182196

183197
if (index >= 2) {
184-
u32 reg_caps, reg_htc;
198+
u32 reg;
199+
200+
if (!data->read_htcreg)
201+
return 0;
185202

186203
pci_read_config_dword(pdev, REG_NORTHBRIDGE_CAPABILITIES,
187-
&reg_caps);
188-
pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL,
189-
&reg_htc);
190-
if (!(reg_caps & NB_CAP_HTC) || !(reg_htc & HTC_ENABLE))
204+
&reg);
205+
if (!(reg & NB_CAP_HTC))
206+
return 0;
207+
208+
data->read_htcreg(data->pdev, &reg);
209+
if (!(reg & HTC_ENABLE))
191210
return 0;
192211
}
193212
return attr->mode;
@@ -268,11 +287,13 @@ static int k10temp_probe(struct pci_dev *pdev,
268287

269288
if (boot_cpu_data.x86 == 0x15 && (boot_cpu_data.x86_model == 0x60 ||
270289
boot_cpu_data.x86_model == 0x70)) {
290+
data->read_htcreg = read_htcreg_nb_f15;
271291
data->read_tempreg = read_tempreg_nb_f15;
272292
} else if (boot_cpu_data.x86 == 0x17) {
273293
data->temp_adjust_mask = 0x80000;
274294
data->read_tempreg = read_tempreg_nb_f17;
275295
} else {
296+
data->read_htcreg = read_htcreg_pci;
276297
data->read_tempreg = read_tempreg_pci;
277298
}
278299

@@ -302,7 +323,7 @@ static const struct pci_device_id k10temp_id_table[] = {
302323
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
303324
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
304325
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
305-
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_RR_NB) },
326+
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
306327
{}
307328
};
308329
MODULE_DEVICE_TABLE(pci, k10temp_id_table);

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