|
141 | 141 | };
|
142 | 142 | };
|
143 | 143 |
|
144 |
| -&cif_isp0 { |
145 |
| - rockchip,camera-modules-attached = |
146 |
| - <&camera0 &camera1 &camera2 &camera3>; |
| 144 | +&rkisp1_0 { |
147 | 145 | status = "okay";
|
| 146 | + |
| 147 | + port { |
| 148 | + #address-cells = <1>; |
| 149 | + #size-cells = <0>; |
| 150 | + |
| 151 | + isp0_mipi_in: endpoint@0 { |
| 152 | + reg = <0>; |
| 153 | + remote-endpoint = <&dphy_rx0_out>; |
| 154 | + }; |
| 155 | + }; |
| 156 | +}; |
| 157 | + |
| 158 | +&mipi_dphy_rx0 { |
| 159 | + status = "okay"; |
| 160 | + |
| 161 | + ports { |
| 162 | + #address-cells = <1>; |
| 163 | + #size-cells = <0>; |
| 164 | + |
| 165 | + port@0 { |
| 166 | + reg = <0>; |
| 167 | + #address-cells = <1>; |
| 168 | + #size-cells = <0>; |
| 169 | + |
| 170 | + mipi_in_ucam0: endpoint@1 { |
| 171 | + reg = <1>; |
| 172 | + remote-endpoint = <&ucam_out0>; |
| 173 | + data-lanes = <1 2>; |
| 174 | + }; |
| 175 | + }; |
| 176 | + |
| 177 | + port@1 { |
| 178 | + reg = <1>; |
| 179 | + #address-cells = <1>; |
| 180 | + #size-cells = <0>; |
| 181 | + |
| 182 | + dphy_rx0_out: endpoint@0 { |
| 183 | + reg = <0>; |
| 184 | + remote-endpoint = <&isp0_mipi_in>; |
| 185 | + }; |
| 186 | + }; |
| 187 | + }; |
148 | 188 | };
|
149 | 189 |
|
150 | 190 | &isp0_mmu {
|
151 | 191 | status = "okay";
|
152 | 192 | };
|
153 | 193 |
|
154 |
| -&cif_isp1 { |
155 |
| - rockchip,camera-modules-attached = <&camera4>; |
| 194 | +&rkisp1_1 { |
156 | 195 | status = "okay";
|
| 196 | + |
| 197 | + port { |
| 198 | + #address-cells = <1>; |
| 199 | + #size-cells = <0>; |
| 200 | + |
| 201 | + isp1_mipi_in: endpoint@0 { |
| 202 | + reg = <0>; |
| 203 | + remote-endpoint = <&dphy_tx1rx1_out>; |
| 204 | + }; |
| 205 | + }; |
| 206 | +}; |
| 207 | + |
| 208 | +&mipi_dphy_tx1rx1 { |
| 209 | + status = "okay"; |
| 210 | + |
| 211 | + ports { |
| 212 | + #address-cells = <1>; |
| 213 | + #size-cells = <0>; |
| 214 | + |
| 215 | + port@0 { |
| 216 | + reg = <0>; |
| 217 | + #address-cells = <1>; |
| 218 | + #size-cells = <0>; |
| 219 | + |
| 220 | + mipi_in_ucam1: endpoint@1 { |
| 221 | + reg = <1>; |
| 222 | + /* Unlinked camera */ |
| 223 | + //remote-endpoint = <&ucam_out1>; |
| 224 | + data-lanes = <1 2>; |
| 225 | + }; |
| 226 | + }; |
| 227 | + |
| 228 | + port@1 { |
| 229 | + reg = <1>; |
| 230 | + #address-cells = <1>; |
| 231 | + #size-cells = <0>; |
| 232 | + |
| 233 | + dphy_tx1rx1_out: endpoint@0 { |
| 234 | + reg = <0>; |
| 235 | + remote-endpoint = <&isp1_mipi_in>; |
| 236 | + }; |
| 237 | + }; |
| 238 | + }; |
157 | 239 | };
|
158 | 240 |
|
159 | 241 | &isp1_mmu {
|
|
227 | 309 | rst_gpio_number = <&gpio4 22 GPIO_ACTIVE_HIGH>;
|
228 | 310 | };
|
229 | 311 |
|
230 |
| - camera0: camera-module@60 { |
231 |
| - status = "okay"; |
232 |
| - compatible = "ovti,ov7750-v4l2-i2c-subdev"; |
233 |
| - reg = < 0x60 >; |
234 |
| - device_type = "v4l2-i2c-subdev"; |
235 |
| - |
236 |
| - clocks = <&cru SCLK_CIF_OUT>; |
237 |
| - clock-names = "clk_cif_out"; |
238 |
| - |
239 |
| - pinctrl-names = "rockchip,camera_default", |
240 |
| - "rockchip,camera_sleep"; |
241 |
| - pinctrl-0 = <&cam0_default_pins>; |
242 |
| - pinctrl-1 = <&cam0_sleep_pins>; |
243 |
| - |
244 |
| - rockchip,pwr-gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>; |
245 |
| - rockchip,camera-module-mclk-name = "clk_cif_out"; |
246 |
| - rockchip,camera-module-facing = "back"; |
247 |
| - rockchip,camera-module-name = "cmk-cb0695-fv1"; |
248 |
| - rockchip,camera-module-len-name = "lg9569a2"; |
249 |
| - rockchip,camera-module-fov-h = "133.0"; |
250 |
| - rockchip,camera-module-fov-v = "100.1"; |
251 |
| - rockchip,camera-module-orientation = <0>; |
252 |
| - rockchip,camera-module-iq-flip = <0>; |
253 |
| - rockchip,camera-module-iq-mirror = <0>; |
254 |
| - rockchip,camera-module-flip = <0>; |
255 |
| - rockchip,camera-module-mirror = <0>; |
256 |
| - |
257 |
| - rockchip,camera-module-defrect0 = <640 480 0 0 640 480>; |
258 |
| - rockchip,camera-module-defrect1 = <640 480 0 0 640 480>; |
259 |
| - rockchip,camera-module-defrect2 = <640 480 0 0 640 480>; |
260 |
| - rockchip,camera-module-defrect3 = <640 480 0 0 640 480>; |
261 |
| - rockchip,camera-module-flash-support = <0>; |
262 |
| - rockchip,camera-module-mipi-dphy-index = <0>; |
263 |
| - }; |
264 |
| - |
265 |
| - camera1: camera-module@1 { |
| 312 | + ov13850: ov13850@10 { |
| 313 | + compatible = "ovti,ov13850"; |
266 | 314 | status = "okay";
|
267 |
| - compatible = "toshiba,tc358749xbg-v4l2-i2c-subdev"; |
268 |
| - reg = < 0x0f >; |
269 |
| - device_type = "v4l2-i2c-subdev"; |
270 |
| - |
271 |
| - clocks = <&cru SCLK_CIF_OUT>; |
272 |
| - clock-names = "clk_cif_out"; |
273 |
| - |
274 |
| - pinctrl-names = "default"; |
275 |
| - pinctrl-0 = <&hdmiin_gpios>; |
276 |
| - |
277 |
| - //rockchip,pwr-gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; |
278 |
| - //rckchip,pwr-snd-gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; |
279 |
| - //rockchip,pwr-trd-gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>; |
280 |
| - //rockchip,rst-gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>; |
281 |
| - power-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; |
282 |
| - power18-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; |
283 |
| - power33-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; |
284 |
| - csi-ctl-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; |
285 |
| - stanby-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; |
286 |
| - reset-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; |
287 |
| - int-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; |
288 |
| - |
289 |
| - rockchip,camera-module-mclk-name = "clk_cif_out"; |
290 |
| - rockchip,camera-module-mipi-dphy-index = <0>; |
291 |
| - }; |
292 |
| - |
293 |
| - camera2: camera-module@10 { |
294 |
| - status = "okay"; |
295 |
| - compatible = "omnivision,ov13850-v4l2-i2c-subdev"; |
296 |
| - reg = < 0x10 >; |
297 |
| - device_type = "v4l2-i2c-subdev"; |
298 |
| - clocks = <&cru SCLK_CIF_OUT>; |
299 |
| - clock-names = "clk_cif_out"; |
300 |
| - pinctrl-names = "rockchip,camera_default", |
301 |
| - "rockchip,camera_sleep"; |
302 |
| - pinctrl-0 = <&cam0_default_pins>; |
303 |
| - pinctrl-1 = <&cam0_sleep_pins>; |
304 |
| - rockchip,pd-gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; |
305 |
| - //rockchip,pwr-gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>; |
306 |
| - /* mipi switch control */ |
307 |
| - rockchip,rst-gpio = <&gpio2 10 GPIO_ACTIVE_LOW>; |
308 |
| - rockchip,camera-module-mclk-name = "clk_cif_out"; |
309 |
| - rockchip,camera-module-facing = "back"; |
310 |
| - rockchip,camera-module-name = "cmk-cb0695-fv1"; |
311 |
| - rockchip,camera-module-len-name = "lg9569a2"; |
312 |
| - rockchip,camera-module-fov-h = "66.0"; |
313 |
| - rockchip,camera-module-fov-v = "50.1"; |
314 |
| - rockchip,camera-module-orientation = <0>; |
315 |
| - rockchip,camera-module-iq-flip = <0>; |
316 |
| - rockchip,camera-module-iq-mirror = <0>; |
317 |
| - rockchip,camera-module-flip = <1>; |
318 |
| - rockchip,camera-module-mirror = <0>; |
319 |
| - |
320 |
| - rockchip,camera-module-defrect0 = <2112 1568 0 0 2112 1568>; |
321 |
| - rockchip,camera-module-defrect1 = <4224 3136 0 0 4224 3136>; |
322 |
| - rockchip,camera-module-defrect3 = <3264 2448 0 0 3264 2448>; |
323 |
| - rockchip,camera-module-flash-support = <1>; |
324 |
| - rockchip,camera-module-mipi-dphy-index = <0>; |
325 |
| - }; |
326 |
| - |
327 |
| - camera3: camera-module@36 { |
328 |
| - status = "okay"; |
329 |
| - compatible = "omnivision,ov4689-v4l2-i2c-subdev"; |
330 |
| - reg = <0x36>; |
331 |
| - device_type = "v4l2-i2c-subdev"; |
| 315 | + reg = <0x10>; |
332 | 316 | clocks = <&cru SCLK_CIF_OUT>;
|
333 |
| - clock-names = "clk_cif_out"; |
334 |
| - pinctrl-names = "rockchip,camera_default", |
335 |
| - "rockchip,camera_sleep"; |
336 |
| - pinctrl-0 = <&cam0_default_pins>; |
337 |
| - pinctrl-1 = <&cam0_sleep_pins>; |
338 |
| - rockchip,pd-gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; |
339 |
| - //rockchip,pwr-gpio = <&gpio3 13 0>; |
340 |
| - /* mipi switch control*/ |
341 |
| - rockchip,rst-gpio = <&gpio2 10 GPIO_ACTIVE_LOW>; |
342 |
| - rockchip,camera-module-mclk-name = "clk_cif_out"; |
343 |
| - rockchip,camera-module-facing = "back"; |
344 |
| - rockchip,camera-module-name = "LA6111PA"; |
345 |
| - rockchip,camera-module-len-name = "YM6011P"; |
346 |
| - rockchip,camera-module-fov-h = "116"; |
347 |
| - rockchip,camera-module-fov-v = "61"; |
348 |
| - rockchip,camera-module-orientation = <0>; |
349 |
| - rockchip,camera-module-iq-flip = <0>; |
350 |
| - rockchip,camera-module-iq-mirror = <0>; |
351 |
| - rockchip,camera-module-flip = <0>; |
352 |
| - rockchip,camera-module-mirror = <1>; |
353 |
| - |
354 |
| - rockchip,camera-module-defrect0 = <2688 1520 0 0 2688 1520>; |
355 |
| - rockchip,camera-module-flash-support = <0>; |
356 |
| - rockchip,camera-module-mipi-dphy-index = <0>; |
| 317 | + clock-names = "xvclk"; |
| 318 | + |
| 319 | + /* conflict with csi-ctl-gpios */ |
| 320 | + reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; |
| 321 | + pwdn-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; |
| 322 | + pinctrl-names = "rockchip,camera_default"; |
| 323 | + pinctrl-0 = <&cif_clkout>; |
| 324 | + |
| 325 | + port { |
| 326 | + ucam_out0: endpoint { |
| 327 | + remote-endpoint = <&mipi_in_ucam0>; |
| 328 | + data-lanes = <1 2>; |
| 329 | + }; |
| 330 | + }; |
357 | 331 | };
|
358 | 332 | };
|
359 | 333 |
|
360 | 334 | &i2c4 {
|
361 | 335 | status = "okay";
|
362 |
| - |
363 |
| - camera4: camera-module@2 { |
364 |
| - status = "okay"; |
365 |
| - compatible = "adi,adv7181-v4l2-i2c-subdev"; |
366 |
| - reg = < 0x21 >; |
367 |
| - device_type = "v4l2-i2c-subdev"; |
368 |
| - |
369 |
| - clocks = <&cru SCLK_CIF_OUT>; |
370 |
| - clock-names = "clk_cif_out"; |
371 |
| - |
372 |
| - pinctrl-names = "rockchip,camera_default", |
373 |
| - "rockchip,camera_sleep"; |
374 |
| - pinctrl-0 = <&isp_dvp_d0d7>; |
375 |
| - pinctrl-1 = <&cam0_sleep_pins>; |
376 |
| - |
377 |
| - rockchip,camera-module-defrect0 = <720 480 0 13 720 480>; |
378 |
| - rockchip,camera-module-defrect1 = <720 576 0 0 720 576>; |
379 |
| - rockchip,camera-module-mclk-name = "clk_cif_out"; |
380 |
| - rockchip,camera-module-mipi-dphy-index = <1>; |
381 |
| - }; |
382 | 336 | };
|
383 | 337 |
|
384 | 338 | &pcie_phy {
|
|
0 commit comments