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Merge branch 'x86-cpufeature-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 cpufeature updates from Ingo Molnar: "The main changes in this cycle were related to enable ring-3 MONITOR/MWAIT instructions support on supported CPUs, by Grzegorz Andrejczuk and Piotr Luc" * 'x86-cpufeature-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/cpufeature: Move RING3MWAIT feature to avoid conflicts x86/cpufeature: Enable RING3MWAIT for Knights Mill x86/cpufeature: Enable RING3MWAIT for Knights Landing x86/cpufeature: Add RING3MWAIT to CPU features x86/elf: Add HWCAP2 to expose ring 3 MONITOR/MWAIT x86/msr: Add MSR_MISC_FEATURE_ENABLES and RING3MWAIT bit x86/cpufeature: Add AVX512_VPOPCNTDQ feature
2 parents 2891e8e + 3bba73b commit 8a9365a

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‎Documentation/admin-guide/kernel-parameters.txt‎

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@@ -3561,6 +3561,10 @@
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rhash_entries= [KNL,NET]
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Set number of hash buckets for route cache
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ring3mwait=disable
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[KNL] Disable ring 3 MONITOR/MWAIT feature on supported
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CPUs.
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ro [KNL] Mount root device read-only on boot
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rodata= [KNL]

‎arch/x86/include/asm/cpufeatures.h‎

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@@ -186,7 +186,7 @@
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*
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* Reuse free bits when adding new feature flags!
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*/
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#define X86_FEATURE_RING3MWAIT ( 7*32+ 0) /* Ring 3 MONITOR/MWAIT */
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#define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */
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#define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */
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#define X86_FEATURE_CAT_L3 ( 7*32+ 4) /* Cache Allocation Technology L3 */
@@ -288,6 +288,7 @@
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#define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/
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#define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */
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#define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */
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#define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */
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#define X86_FEATURE_RDPID (16*32+ 22) /* RDPID instruction */
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/* AMD-defined CPU features, CPUID level 0x80000007 (ebx), word 17 */
@@ -320,5 +321,4 @@
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#define X86_BUG_SWAPGS_FENCE X86_BUG(11) /* SWAPGS without input dep on GS */
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#define X86_BUG_MONITOR X86_BUG(12) /* IPI required to wake up remote CPU */
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#define X86_BUG_AMD_E400 X86_BUG(13) /* CPU is among the affected by Erratum 400 */
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#endif /* _ASM_X86_CPUFEATURES_H */

‎arch/x86/include/asm/elf.h‎

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@@ -258,6 +258,15 @@ extern int force_personality32;
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#define ELF_HWCAP (boot_cpu_data.x86_capability[CPUID_1_EDX])
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extern u32 elf_hwcap2;
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/*
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* HWCAP2 supplies mask with kernel enabled CPU features, so that
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* the application can discover that it can safely use them.
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* The bits are defined in uapi/asm/hwcap2.h.
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*/
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#define ELF_HWCAP2 (elf_hwcap2)
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/* This yields a string that ld.so will use to load implementation
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specific libraries for optimization. This is more specific in
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intent than poking at uname or /proc/cpuinfo.

‎arch/x86/include/asm/msr-index.h‎

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@@ -543,6 +543,11 @@
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#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39
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#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
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/* MISC_FEATURE_ENABLES non-architectural features */
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#define MSR_MISC_FEATURE_ENABLES 0x00000140
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#define MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT 1
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#define MSR_IA32_TSC_DEADLINE 0x000006E0
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/* P4/Xeon+ specific */

‎arch/x86/include/uapi/asm/hwcap2.h‎

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@@ -0,0 +1,7 @@
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#ifndef _ASM_X86_HWCAP2_H
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#define _ASM_X86_HWCAP2_H
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/* MONITOR/MWAIT enabled in Ring 3 */
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#define HWCAP2_RING3MWAIT (1 << 0)
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#endif

‎arch/x86/kernel/cpu/common.c‎

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@@ -35,6 +35,7 @@
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#include <asm/desc.h>
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#include <asm/fpu/internal.h>
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#include <asm/mtrr.h>
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#include <asm/hwcap2.h>
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#include <linux/numa.h>
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#include <asm/asm.h>
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#include <asm/bugs.h>
@@ -51,6 +52,8 @@
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#include "cpu.h"
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u32 elf_hwcap2 __read_mostly;
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/* all of these masks are initialized in setup_cpu_local_masks() */
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cpumask_var_t cpu_initialized_mask;
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cpumask_var_t cpu_callout_mask;

‎arch/x86/kernel/cpu/intel.c‎

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@@ -15,6 +15,8 @@
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#include <asm/cpu.h>
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#include <asm/intel-family.h>
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#include <asm/microcode_intel.h>
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#include <asm/hwcap2.h>
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#include <asm/elf.h>
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#ifdef CONFIG_X86_64
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#include <linux/topology.h>
@@ -62,6 +64,46 @@ void check_mpx_erratum(struct cpuinfo_x86 *c)
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}
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}
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static bool ring3mwait_disabled __read_mostly;
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static int __init ring3mwait_disable(char *__unused)
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{
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ring3mwait_disabled = true;
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return 0;
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}
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__setup("ring3mwait=disable", ring3mwait_disable);
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static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
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{
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/*
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* Ring 3 MONITOR/MWAIT feature cannot be detected without
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* cpu model and family comparison.
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*/
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if (c->x86 != 6)
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return;
84+
switch (c->x86_model) {
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case INTEL_FAM6_XEON_PHI_KNL:
86+
case INTEL_FAM6_XEON_PHI_KNM:
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break;
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default:
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return;
90+
}
91+
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if (ring3mwait_disabled) {
93+
msr_clear_bit(MSR_MISC_FEATURE_ENABLES,
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MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT);
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return;
96+
}
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msr_set_bit(MSR_MISC_FEATURE_ENABLES,
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MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT);
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set_cpu_cap(c, X86_FEATURE_RING3MWAIT);
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if (c == &boot_cpu_data)
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ELF_HWCAP2 |= HWCAP2_RING3MWAIT;
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}
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static void early_init_intel(struct cpuinfo_x86 *c)
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{
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u64 misc_enable;
@@ -562,6 +604,8 @@ static void init_intel(struct cpuinfo_x86 *c)
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detect_vmx_virtcap(c);
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init_intel_energy_perf(c);
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probe_xeon_phi_r3mwait(c);
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}
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#ifdef CONFIG_X86_32

‎arch/x86/kernel/fpu/xstate.c‎

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@@ -78,6 +78,7 @@ void fpu__xstate_clear_all_cpu_caps(void)
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setup_clear_cpu_cap(X86_FEATURE_PKU);
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setup_clear_cpu_cap(X86_FEATURE_AVX512_4VNNIW);
8080
setup_clear_cpu_cap(X86_FEATURE_AVX512_4FMAPS);
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setup_clear_cpu_cap(X86_FEATURE_AVX512_VPOPCNTDQ);
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}
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/*

‎tools/arch/x86/include/asm/cpufeatures.h‎

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@@ -288,6 +288,7 @@
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#define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/
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#define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */
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#define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */
291+
#define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */
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#define X86_FEATURE_RDPID (16*32+ 22) /* RDPID instruction */
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293294
/* AMD-defined CPU features, CPUID level 0x80000007 (ebx), word 17 */

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