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stefanchulskidavem330
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net: mvpp2: add TX FC firmware check
Patch check that TX FC firmware is running in CM3. If not, global TX FC would be disabled. Signed-off-by: Stefan Chulski <[email protected]> Acked-by: Marcin Wojtas <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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+33
-7
lines changed

2 files changed

+33
-7
lines changed

drivers/net/ethernet/marvell/mvpp2/mvpp2.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -828,6 +828,7 @@
828828

829829
#define MSS_THRESHOLD_STOP 768
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#define MSS_THRESHOLD_START 1024
831+
#define MSS_FC_MAX_TIMEOUT 5000
831832

832833
/* RX buffer constants */
833834
#define MVPP2_SKB_SHINFO_SIZE \

drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c

Lines changed: 32 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -924,6 +924,34 @@ static void mvpp2_bm_pool_update_fc(struct mvpp2_port *port,
924924
spin_unlock_irqrestore(&port->priv->mss_spinlock, flags);
925925
}
926926

927+
static int mvpp2_enable_global_fc(struct mvpp2 *priv)
928+
{
929+
int val, timeout = 0;
930+
931+
/* Enable global flow control. In this stage global
932+
* flow control enabled, but still disabled per port.
933+
*/
934+
val = mvpp2_cm3_read(priv, MSS_FC_COM_REG);
935+
val |= FLOW_CONTROL_ENABLE_BIT;
936+
mvpp2_cm3_write(priv, MSS_FC_COM_REG, val);
937+
938+
/* Check if Firmware running and disable FC if not*/
939+
val |= FLOW_CONTROL_UPDATE_COMMAND_BIT;
940+
mvpp2_cm3_write(priv, MSS_FC_COM_REG, val);
941+
942+
while (timeout < MSS_FC_MAX_TIMEOUT) {
943+
val = mvpp2_cm3_read(priv, MSS_FC_COM_REG);
944+
945+
if (!(val & FLOW_CONTROL_UPDATE_COMMAND_BIT))
946+
return 0;
947+
usleep_range(10, 20);
948+
timeout++;
949+
}
950+
951+
priv->global_tx_fc = false;
952+
return -EOPNOTSUPP;
953+
}
954+
927955
/* Release buffer to BM */
928956
static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
929957
dma_addr_t buf_dma_addr,
@@ -7264,7 +7292,7 @@ static int mvpp2_probe(struct platform_device *pdev)
72647292
struct resource *res;
72657293
void __iomem *base;
72667294
int i, shared;
7267-
int err, val;
7295+
int err;
72687296

72697297
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
72707298
if (!priv)
@@ -7488,13 +7516,10 @@ static int mvpp2_probe(struct platform_device *pdev)
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goto err_port_probe;
74897517
}
74907518

7491-
/* Enable global flow control. In this stage global
7492-
* flow control enabled, but still disabled per port.
7493-
*/
74947519
if (priv->global_tx_fc && priv->hw_version != MVPP21) {
7495-
val = mvpp2_cm3_read(priv, MSS_FC_COM_REG);
7496-
val |= FLOW_CONTROL_ENABLE_BIT;
7497-
mvpp2_cm3_write(priv, MSS_FC_COM_REG, val);
7520+
err = mvpp2_enable_global_fc(priv);
7521+
if (err)
7522+
dev_warn(&pdev->dev, "Minimum of CM3 firmware 18.09 and chip revision B0 required for flow control\n");
74987523
}
74997524

75007525
mvpp2_dbgfs_init(priv, pdev->name);

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