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davem330davem330
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Merge branch 'GEHC-Bx50-Switch-Support'
Sebastian Reichel says: ==================== GEHC Bx50 Switch Support This adds support for the internal switch found in GE Healthcare B450v3, B650v3 and B850v3. All devices use a GPIO bitbanged MDIO bus to communicate with the switch and a PCIe based network card for exchanging network data. The cpu network data link requires, that the switch's internal phy interface is enabled, so support for that is added by the first patch in this series. The patch series is based on v4.15-rc8. Changes since PATCHv4: * Introduce dsa_port_link_(un)register_of and mark the fixed variant static. * Update patch description to describe the phy<->phy connection from i210 to the Marvell switch Changes since PATCHv3: * Enable the phy in dsa_port_setup() instead of abusing the fixed link setup function Changes since PATCHv2: * Add phy nodes to switch in bx50.dtsi and reference them from switch ports * Enable cpu-port's phy based on 'phy-handle' instead of 'phy-mode' Changes since PATCHv1: * Use 'marvell,mv88e6085' instead of introducing compatible string for mv88e6240. * Fix indention of DT nodes * Only enable 'cpu' phy, if explicitly set to "internal". ==================== Signed-off-by: David S. Miller <[email protected]>
2 parents 5ca1144 + 658d063 commit c89b517

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‎arch/arm/boot/dts/imx6q-b450v3.dts‎

Lines changed: 52 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -112,3 +112,55 @@
112112
line-name = "PCA9539-P07";
113113
};
114114
};
115+
116+
&pci_root {
117+
/* Intel Corporation I210 Gigabit Network Connection */
118+
switch_nic: ethernet@3,0 {
119+
compatible = "pci8086,1533";
120+
reg = <0x00010000 0 0 0 0>;
121+
};
122+
};
123+
124+
&switch_ports {
125+
port@0 {
126+
reg = <0>;
127+
label = "enacq";
128+
phy-handle = <&switchphy0>;
129+
};
130+
131+
port@1 {
132+
reg = <1>;
133+
label = "eneport1";
134+
phy-handle = <&switchphy1>;
135+
};
136+
137+
port@2 {
138+
reg = <2>;
139+
label = "enix";
140+
phy-handle = <&switchphy2>;
141+
};
142+
143+
port@3 {
144+
reg = <3>;
145+
label = "enid";
146+
phy-handle = <&switchphy3>;
147+
};
148+
149+
port@4 {
150+
reg = <4>;
151+
label = "cpu";
152+
ethernet = <&switch_nic>;
153+
phy-handle = <&switchphy4>;
154+
};
155+
156+
port@5 {
157+
reg = <5>;
158+
label = "enembc";
159+
160+
/* connected to Ethernet MAC of AT91RM9200 in MII mode */
161+
fixed-link {
162+
speed = <100>;
163+
full-duplex;
164+
};
165+
};
166+
};

‎arch/arm/boot/dts/imx6q-b650v3.dts‎

Lines changed: 52 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -111,3 +111,55 @@
111111
fsl,tx-cal-45-dp-ohms = <55>;
112112
fsl,tx-d-cal = <100>;
113113
};
114+
115+
&pci_root {
116+
/* Intel Corporation I210 Gigabit Network Connection */
117+
switch_nic: ethernet@3,0 {
118+
compatible = "pci8086,1533";
119+
reg = <0x00010000 0 0 0 0>;
120+
};
121+
};
122+
123+
&switch_ports {
124+
port@0 {
125+
reg = <0>;
126+
label = "enacq";
127+
phy-handle = <&switchphy0>;
128+
};
129+
130+
port@1 {
131+
reg = <1>;
132+
label = "eneport1";
133+
phy-handle = <&switchphy1>;
134+
};
135+
136+
port@2 {
137+
reg = <2>;
138+
label = "enix";
139+
phy-handle = <&switchphy2>;
140+
};
141+
142+
port@3 {
143+
reg = <3>;
144+
label = "enid";
145+
phy-handle = <&switchphy3>;
146+
};
147+
148+
port@4 {
149+
reg = <4>;
150+
label = "cpu";
151+
ethernet = <&switch_nic>;
152+
phy-handle = <&switchphy4>;
153+
};
154+
155+
port@5 {
156+
reg = <5>;
157+
label = "enembc";
158+
159+
/* connected to Ethernet MAC of AT91RM9200 in MII mode */
160+
fixed-link {
161+
speed = <100>;
162+
full-duplex;
163+
};
164+
};
165+
};

‎arch/arm/boot/dts/imx6q-b850v3.dts‎

Lines changed: 75 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -212,3 +212,78 @@
212212
};
213213
};
214214
};
215+
216+
&pci_root {
217+
/* PLX Technology, Inc. PEX 8605 PCI Express 4-port Gen2 Switch */
218+
bridge@1,0 {
219+
compatible = "pci10b5,8605";
220+
reg = <0x00010000 0 0 0 0>;
221+
222+
#address-cells = <3>;
223+
#size-cells = <2>;
224+
#interrupt-cells = <1>;
225+
226+
bridge@2,1 {
227+
compatible = "pci10b5,8605";
228+
reg = <0x00020800 0 0 0 0>;
229+
230+
#address-cells = <3>;
231+
#size-cells = <2>;
232+
#interrupt-cells = <1>;
233+
234+
/* Intel Corporation I210 Gigabit Network Connection */
235+
ethernet@3,0 {
236+
compatible = "pci8086,1533";
237+
reg = <0x00030000 0 0 0 0>;
238+
};
239+
};
240+
241+
bridge@2,2 {
242+
compatible = "pci10b5,8605";
243+
reg = <0x00021000 0 0 0 0>;
244+
245+
#address-cells = <3>;
246+
#size-cells = <2>;
247+
#interrupt-cells = <1>;
248+
249+
/* Intel Corporation I210 Gigabit Network Connection */
250+
switch_nic: ethernet@4,0 {
251+
compatible = "pci8086,1533";
252+
reg = <0x00040000 0 0 0 0>;
253+
};
254+
};
255+
};
256+
};
257+
258+
&switch_ports {
259+
port@0 {
260+
reg = <0>;
261+
label = "eneport1";
262+
phy-handle = <&switchphy0>;
263+
};
264+
265+
port@1 {
266+
reg = <1>;
267+
label = "eneport2";
268+
phy-handle = <&switchphy1>;
269+
};
270+
271+
port@2 {
272+
reg = <2>;
273+
label = "enix";
274+
phy-handle = <&switchphy2>;
275+
};
276+
277+
port@3 {
278+
reg = <3>;
279+
label = "enid";
280+
phy-handle = <&switchphy3>;
281+
};
282+
283+
port@4 {
284+
reg = <4>;
285+
label = "cpu";
286+
ethernet = <&switch_nic>;
287+
phy-handle = <&switchphy4>;
288+
};
289+
};

‎arch/arm/boot/dts/imx6q-bx50v3.dtsi‎

Lines changed: 62 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -92,6 +92,56 @@
9292
mux-int-port = <1>;
9393
mux-ext-port = <4>;
9494
};
95+
96+
aliases {
97+
mdio-gpio0 = &mdio0;
98+
};
99+
100+
mdio0: mdio-gpio {
101+
compatible = "virtual,mdio-gpio";
102+
gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>, /* mdc */
103+
<&gpio2 7 GPIO_ACTIVE_HIGH>; /* mdio */
104+
105+
#address-cells = <1>;
106+
#size-cells = <0>;
107+
108+
switch@0 {
109+
compatible = "marvell,mv88e6085"; /* 88e6240*/
110+
#address-cells = <1>;
111+
#size-cells = <0>;
112+
reg = <0>;
113+
114+
switch_ports: ports {
115+
#address-cells = <1>;
116+
#size-cells = <0>;
117+
};
118+
119+
mdio {
120+
#address-cells = <1>;
121+
#size-cells = <0>;
122+
123+
switchphy0: switchphy@0 {
124+
reg = <0>;
125+
};
126+
127+
switchphy1: switchphy@1 {
128+
reg = <1>;
129+
};
130+
131+
switchphy2: switchphy@2 {
132+
reg = <2>;
133+
};
134+
135+
switchphy3: switchphy@3 {
136+
reg = <3>;
137+
};
138+
139+
switchphy4: switchphy@4 {
140+
reg = <4>;
141+
};
142+
};
143+
};
144+
};
95145
};
96146

97147
&ecspi5 {
@@ -326,3 +376,15 @@
326376
tcxo-clock-frequency = <26000000>;
327377
};
328378
};
379+
380+
&pcie {
381+
/* Synopsys, Inc. Device */
382+
pci_root: root@0,0 {
383+
compatible = "pci16c3,abcd";
384+
reg = <0x00000000 0 0 0 0>;
385+
386+
#address-cells = <3>;
387+
#size-cells = <2>;
388+
#interrupt-cells = <1>;
389+
};
390+
};

‎net/dsa/dsa2.c‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -271,13 +271,12 @@ static int dsa_port_setup(struct dsa_port *dp)
271271
break;
272272
case DSA_PORT_TYPE_CPU:
273273
case DSA_PORT_TYPE_DSA:
274-
err = dsa_port_fixed_link_register_of(dp);
274+
err = dsa_port_link_register_of(dp);
275275
if (err) {
276-
dev_err(ds->dev, "failed to register fixed link for port %d.%d\n",
276+
dev_err(ds->dev, "failed to setup link for port %d.%d\n",
277277
ds->index, dp->index);
278278
return err;
279279
}
280-
281280
break;
282281
case DSA_PORT_TYPE_USER:
283282
err = dsa_slave_create(dp);
@@ -301,7 +300,7 @@ static void dsa_port_teardown(struct dsa_port *dp)
301300
break;
302301
case DSA_PORT_TYPE_CPU:
303302
case DSA_PORT_TYPE_DSA:
304-
dsa_port_fixed_link_unregister_of(dp);
303+
dsa_port_link_unregister_of(dp);
305304
break;
306305
case DSA_PORT_TYPE_USER:
307306
if (dp->slave) {

‎net/dsa/dsa_priv.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -166,8 +166,8 @@ int dsa_port_vlan_add(struct dsa_port *dp,
166166
struct switchdev_trans *trans);
167167
int dsa_port_vlan_del(struct dsa_port *dp,
168168
const struct switchdev_obj_port_vlan *vlan);
169-
int dsa_port_fixed_link_register_of(struct dsa_port *dp);
170-
void dsa_port_fixed_link_unregister_of(struct dsa_port *dp);
169+
int dsa_port_link_register_of(struct dsa_port *dp);
170+
void dsa_port_link_unregister_of(struct dsa_port *dp);
171171

172172
/* slave.c */
173173
extern const struct dsa_device_ops notag_netdev_ops;

‎net/dsa/legacy.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -86,7 +86,7 @@ static int dsa_cpu_dsa_setups(struct dsa_switch *ds)
8686
if (!(dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)))
8787
continue;
8888

89-
ret = dsa_port_fixed_link_register_of(&ds->ports[port]);
89+
ret = dsa_port_link_register_of(&ds->ports[port]);
9090
if (ret)
9191
return ret;
9292
}
@@ -275,7 +275,7 @@ static void dsa_switch_destroy(struct dsa_switch *ds)
275275
for (port = 0; port < ds->num_ports; port++) {
276276
if (!(dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)))
277277
continue;
278-
dsa_port_fixed_link_unregister_of(&ds->ports[port]);
278+
dsa_port_link_unregister_of(&ds->ports[port]);
279279
}
280280

281281
if (ds->slave_mii_bus && ds->ops->phy_read)

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