Skip to content

Commit d0f7de9

Browse files
committed
Merge tag 'samsung-dt64-4.11-3' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/late
Pull "Samsung DeviceTree ARM64 update for v4.11, third round" from Krzysztof Kozłowski: 1. Add necessary initial configuration for clocks of display subsystem. Till now it worked mostly thanks to bootloader. 2. Use macro definitions instead of hard-coded values for pinctrl on Exynos7. 3. Enable USB 3.0 (DWC3) on Exynos7. * tag 'samsung-dt64-4.11-3' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (27 commits) arm64: dts: exynos: Add regulators for Vbus and Vbus-Boost arm64: dts: exynos: Add USB 3.0 controller node for Exynos7 arm64: dts: exynos: Use macros for pinctrl configuration on Exynos7 pinctrl: dt-bindings: samsung: Add Exynos7 specific pinctrl macro definitions arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks arm64: dts: exynos: Add clocks to Exynos5433 LPASS module arm64: dts: exynos: set LDO7 regulator as always on arm64: dts: exynos: configure TV path clocks for Ultra HD modes arm64: dts: exynos: Fix drive strength of sd0_xxx pin definitions arm64: dts: exynos: Disable pull down for audio pins in Exynos5433 SoCs arm64: dts: exynos: Add TM2 touchkey node arm64: dts: exynos: Remove unneeded unit names in Exynos5433 nodes arm64: dts: exynos: Enable HDMI/TV path on Exynos5433-TM2 arm64: dts: exynos: Add HDMI node to Exynos5433 arm64: dts: exynos: Add DECON_TV node to Exynos5433 arm64: dts: exynos: Fix addresses in node names on Exynos5433 arm64: dts: exynos: Make TM2 and TM2E independent from each other arm64: dts: exynos: Fix wrong values for ldo23 and ldo25 on TM2/TM2E ...
2 parents a121103 + 6629490 commit d0f7de9

File tree

12 files changed

+2036
-1397
lines changed

12 files changed

+2036
-1397
lines changed
Lines changed: 197 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,197 @@
1+
/*
2+
* Samsung's Exynos5433 SoC Memory interface and AMBA bus device tree source
3+
*
4+
* Copyright (c) 2016 Samsung Electronics Co., Ltd.
5+
* Chanwoo Choi <[email protected]>
6+
*
7+
* This program is free software; you can redistribute it and/or modify
8+
* it under the terms of the GNU General Public License version 2 as
9+
* published by the Free Software Foundation.
10+
*/
11+
12+
&soc {
13+
bus_g2d_400: bus0 {
14+
compatible = "samsung,exynos-bus";
15+
clocks = <&cmu_top CLK_ACLK_G2D_400>;
16+
clock-names = "bus";
17+
operating-points-v2 = <&bus_g2d_400_opp_table>;
18+
status = "disabled";
19+
};
20+
21+
bus_g2d_266: bus1 {
22+
compatible = "samsung,exynos-bus";
23+
clocks = <&cmu_top CLK_ACLK_G2D_266>;
24+
clock-names = "bus";
25+
operating-points-v2 = <&bus_g2d_266_opp_table>;
26+
status = "disabled";
27+
};
28+
29+
bus_gscl: bus2 {
30+
compatible = "samsung,exynos-bus";
31+
clocks = <&cmu_top CLK_ACLK_GSCL_333>;
32+
clock-names = "bus";
33+
operating-points-v2 = <&bus_gscl_opp_table>;
34+
status = "disabled";
35+
};
36+
37+
bus_hevc: bus3 {
38+
compatible = "samsung,exynos-bus";
39+
clocks = <&cmu_top CLK_ACLK_HEVC_400>;
40+
clock-names = "bus";
41+
operating-points-v2 = <&bus_hevc_opp_table>;
42+
status = "disabled";
43+
};
44+
45+
bus_jpeg: bus4 {
46+
compatible = "samsung,exynos-bus";
47+
clocks = <&cmu_top CLK_SCLK_JPEG_MSCL>;
48+
clock-names = "bus";
49+
operating-points-v2 = <&bus_g2d_400_opp_table>;
50+
status = "disabled";
51+
};
52+
53+
bus_mfc: bus5 {
54+
compatible = "samsung,exynos-bus";
55+
clocks = <&cmu_top CLK_ACLK_MFC_400>;
56+
clock-names = "bus";
57+
operating-points-v2 = <&bus_g2d_400_opp_table>;
58+
status = "disabled";
59+
};
60+
61+
bus_mscl: bus6 {
62+
compatible = "samsung,exynos-bus";
63+
clocks = <&cmu_top CLK_ACLK_MSCL_400>;
64+
clock-names = "bus";
65+
operating-points-v2 = <&bus_g2d_400_opp_table>;
66+
status = "disabled";
67+
};
68+
69+
bus_noc0: bus7 {
70+
compatible = "samsung,exynos-bus";
71+
clocks = <&cmu_top CLK_ACLK_BUS0_400>;
72+
clock-names = "bus";
73+
operating-points-v2 = <&bus_hevc_opp_table>;
74+
status = "disabled";
75+
};
76+
77+
bus_noc1: bus8 {
78+
compatible = "samsung,exynos-bus";
79+
clocks = <&cmu_top CLK_ACLK_BUS1_400>;
80+
clock-names = "bus";
81+
operating-points-v2 = <&bus_hevc_opp_table>;
82+
status = "disabled";
83+
};
84+
85+
bus_noc2: bus9 {
86+
compatible = "samsung,exynos-bus";
87+
clocks = <&cmu_mif CLK_ACLK_BUS2_400>;
88+
clock-names = "bus";
89+
operating-points-v2 = <&bus_noc2_opp_table>;
90+
status = "disabled";
91+
};
92+
93+
bus_g2d_400_opp_table: opp_table2 {
94+
compatible = "operating-points-v2";
95+
opp-shared;
96+
97+
opp@400000000 {
98+
opp-hz = /bits/ 64 <400000000>;
99+
opp-microvolt = <1075000>;
100+
};
101+
opp@267000000 {
102+
opp-hz = /bits/ 64 <267000000>;
103+
opp-microvolt = <1000000>;
104+
};
105+
opp@200000000 {
106+
opp-hz = /bits/ 64 <200000000>;
107+
opp-microvolt = <975000>;
108+
};
109+
opp@160000000 {
110+
opp-hz = /bits/ 64 <160000000>;
111+
opp-microvolt = <962500>;
112+
};
113+
opp@134000000 {
114+
opp-hz = /bits/ 64 <134000000>;
115+
opp-microvolt = <950000>;
116+
};
117+
opp@100000000 {
118+
opp-hz = /bits/ 64 <100000000>;
119+
opp-microvolt = <937500>;
120+
};
121+
};
122+
123+
bus_g2d_266_opp_table: opp_table3 {
124+
compatible = "operating-points-v2";
125+
126+
opp@267000000 {
127+
opp-hz = /bits/ 64 <267000000>;
128+
};
129+
opp@200000000 {
130+
opp-hz = /bits/ 64 <200000000>;
131+
};
132+
opp@160000000 {
133+
opp-hz = /bits/ 64 <160000000>;
134+
};
135+
opp@134000000 {
136+
opp-hz = /bits/ 64 <134000000>;
137+
};
138+
opp@100000000 {
139+
opp-hz = /bits/ 64 <100000000>;
140+
};
141+
};
142+
143+
bus_gscl_opp_table: opp_table4 {
144+
compatible = "operating-points-v2";
145+
146+
opp@333000000 {
147+
opp-hz = /bits/ 64 <333000000>;
148+
};
149+
opp@222000000 {
150+
opp-hz = /bits/ 64 <222000000>;
151+
};
152+
opp@166500000 {
153+
opp-hz = /bits/ 64 <166500000>;
154+
};
155+
};
156+
157+
bus_hevc_opp_table: opp_table5 {
158+
compatible = "operating-points-v2";
159+
opp-shared;
160+
161+
opp@400000000 {
162+
opp-hz = /bits/ 64 <400000000>;
163+
};
164+
opp@267000000 {
165+
opp-hz = /bits/ 64 <267000000>;
166+
};
167+
opp@200000000 {
168+
opp-hz = /bits/ 64 <200000000>;
169+
};
170+
opp@160000000 {
171+
opp-hz = /bits/ 64 <160000000>;
172+
};
173+
opp@134000000 {
174+
opp-hz = /bits/ 64 <134000000>;
175+
};
176+
opp@100000000 {
177+
opp-hz = /bits/ 64 <100000000>;
178+
};
179+
};
180+
181+
bus_noc2_opp_table: opp_table6 {
182+
compatible = "operating-points-v2";
183+
184+
opp@400000000 {
185+
opp-hz = /bits/ 64 <400000000>;
186+
};
187+
opp@200000000 {
188+
opp-hz = /bits/ 64 <200000000>;
189+
};
190+
opp@134000000 {
191+
opp-hz = /bits/ 64 <134000000>;
192+
};
193+
opp@100000000 {
194+
opp-hz = /bits/ 64 <100000000>;
195+
};
196+
};
197+
};

0 commit comments

Comments
 (0)