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* - v7/v8 long-descriptor format
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* - Non-secure access to the SMMU
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* - Context fault reporting
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+ * - Extended Stream ID (16 bit)
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*/
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#define pr_fmt (fmt ) "arm-smmu: " fmt
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#define sCR0_CLIENTPD (1 << 0)
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#define sCR0_GFRE (1 << 1)
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#define sCR0_GFIE (1 << 2)
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+ #define sCR0_EXIDENABLE (1 << 3)
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#define sCR0_GCFGFRE (1 << 4)
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#define sCR0_GCFGFIE (1 << 5)
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#define sCR0_USFCFG (1 << 10)
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#define ID0_NUMIRPT_MASK 0xff
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#define ID0_NUMSIDB_SHIFT 9
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#define ID0_NUMSIDB_MASK 0xf
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+ #define ID0_EXIDS (1 << 8)
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#define ID0_NUMSMRG_SHIFT 0
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#define ID0_NUMSMRG_MASK 0xff
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#define ARM_SMMU_GR0_S2CR (n ) (0xc00 + ((n) << 2))
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#define S2CR_CBNDX_SHIFT 0
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#define S2CR_CBNDX_MASK 0xff
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+ #define S2CR_EXIDVALID (1 << 10)
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#define S2CR_TYPE_SHIFT 16
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#define S2CR_TYPE_MASK 0x3
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enum arm_smmu_s2cr_type {
@@ -351,6 +355,7 @@ struct arm_smmu_device {
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#define ARM_SMMU_FEAT_FMT_AARCH64_64K (1 << 9)
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#define ARM_SMMU_FEAT_FMT_AARCH32_L (1 << 10)
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#define ARM_SMMU_FEAT_FMT_AARCH32_S (1 << 11)
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+ #define ARM_SMMU_FEAT_EXIDS (1 << 12)
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u32 features ;
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#define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0)
@@ -1048,7 +1053,7 @@ static void arm_smmu_write_smr(struct arm_smmu_device *smmu, int idx)
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struct arm_smmu_smr * smr = smmu -> smrs + idx ;
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u32 reg = smr -> id << SMR_ID_SHIFT | smr -> mask << SMR_MASK_SHIFT ;
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- if (smr -> valid )
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+ if (!( smmu -> features & ARM_SMMU_FEAT_EXIDS ) && smr -> valid )
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reg |= SMR_VALID ;
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writel_relaxed (reg , ARM_SMMU_GR0 (smmu ) + ARM_SMMU_GR0_SMR (idx ));
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}
@@ -1060,6 +1065,9 @@ static void arm_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx)
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(s2cr -> cbndx & S2CR_CBNDX_MASK ) << S2CR_CBNDX_SHIFT |
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(s2cr -> privcfg & S2CR_PRIVCFG_MASK ) << S2CR_PRIVCFG_SHIFT ;
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+ if (smmu -> features & ARM_SMMU_FEAT_EXIDS && smmu -> smrs &&
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+ smmu -> smrs [idx ].valid )
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+ reg |= S2CR_EXIDVALID ;
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writel_relaxed (reg , ARM_SMMU_GR0 (smmu ) + ARM_SMMU_GR0_S2CR (idx ));
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}
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@@ -1070,6 +1078,34 @@ static void arm_smmu_write_sme(struct arm_smmu_device *smmu, int idx)
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arm_smmu_write_smr (smmu , idx );
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}
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+ /*
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+ * The width of SMR's mask field depends on sCR0_EXIDENABLE, so this function
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+ * should be called after sCR0 is written.
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+ */
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+ static void arm_smmu_test_smr_masks (struct arm_smmu_device * smmu )
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+ {
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+ void __iomem * gr0_base = ARM_SMMU_GR0 (smmu );
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+ u32 smr ;
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+
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+ if (!smmu -> smrs )
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+ return ;
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+
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+ /*
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+ * SMR.ID bits may not be preserved if the corresponding MASK
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+ * bits are set, so check each one separately. We can reject
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+ * masters later if they try to claim IDs outside these masks.
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+ */
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+ smr = smmu -> streamid_mask << SMR_ID_SHIFT ;
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+ writel_relaxed (smr , gr0_base + ARM_SMMU_GR0_SMR (0 ));
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+ smr = readl_relaxed (gr0_base + ARM_SMMU_GR0_SMR (0 ));
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+ smmu -> streamid_mask = smr >> SMR_ID_SHIFT ;
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+
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+ smr = smmu -> streamid_mask << SMR_MASK_SHIFT ;
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+ writel_relaxed (smr , gr0_base + ARM_SMMU_GR0_SMR (0 ));
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+ smr = readl_relaxed (gr0_base + ARM_SMMU_GR0_SMR (0 ));
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+ smmu -> smr_mask_mask = smr >> SMR_MASK_SHIFT ;
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+ }
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+
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static int arm_smmu_find_sme (struct arm_smmu_device * smmu , u16 id , u16 mask )
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{
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struct arm_smmu_smr * smrs = smmu -> smrs ;
@@ -1648,6 +1684,9 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
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if (smmu -> features & ARM_SMMU_FEAT_VMID16 )
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reg |= sCR0_VMID16EN ;
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+ if (smmu -> features & ARM_SMMU_FEAT_EXIDS )
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+ reg |= sCR0_EXIDENABLE ;
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+
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/* Push the button */
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__arm_smmu_tlb_sync (smmu );
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writel (reg , ARM_SMMU_GR0_NS (smmu ) + ARM_SMMU_GR0_sCR0 );
@@ -1735,11 +1774,14 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
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"\t(IDR0.CTTW overridden by FW configuration)\n" );
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/* Max. number of entries we have for stream matching/indexing */
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- size = 1 << ((id >> ID0_NUMSIDB_SHIFT ) & ID0_NUMSIDB_MASK );
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+ if (smmu -> version == ARM_SMMU_V2 && id & ID0_EXIDS ) {
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+ smmu -> features |= ARM_SMMU_FEAT_EXIDS ;
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+ size = 1 << 16 ;
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+ } else {
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+ size = 1 << ((id >> ID0_NUMSIDB_SHIFT ) & ID0_NUMSIDB_MASK );
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+ }
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smmu -> streamid_mask = size - 1 ;
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if (id & ID0_SMS ) {
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- u32 smr ;
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-
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smmu -> features |= ARM_SMMU_FEAT_STREAM_MATCH ;
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size = (id >> ID0_NUMSMRG_SHIFT ) & ID0_NUMSMRG_MASK ;
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if (size == 0 ) {
@@ -1748,30 +1790,14 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
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return - ENODEV ;
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}
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- /*
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- * SMR.ID bits may not be preserved if the corresponding MASK
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- * bits are set, so check each one separately. We can reject
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- * masters later if they try to claim IDs outside these masks.
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- */
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- smr = smmu -> streamid_mask << SMR_ID_SHIFT ;
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- writel_relaxed (smr , gr0_base + ARM_SMMU_GR0_SMR (0 ));
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- smr = readl_relaxed (gr0_base + ARM_SMMU_GR0_SMR (0 ));
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- smmu -> streamid_mask = smr >> SMR_ID_SHIFT ;
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-
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- smr = smmu -> streamid_mask << SMR_MASK_SHIFT ;
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- writel_relaxed (smr , gr0_base + ARM_SMMU_GR0_SMR (0 ));
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- smr = readl_relaxed (gr0_base + ARM_SMMU_GR0_SMR (0 ));
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- smmu -> smr_mask_mask = smr >> SMR_MASK_SHIFT ;
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-
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/* Zero-initialised to mark as invalid */
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smmu -> smrs = devm_kcalloc (smmu -> dev , size , sizeof (* smmu -> smrs ),
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GFP_KERNEL );
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if (!smmu -> smrs )
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return - ENOMEM ;
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dev_notice (smmu -> dev ,
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- "\tstream matching with %lu register groups, mask 0x%x" ,
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- size , smmu -> smr_mask_mask );
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+ "\tstream matching with %lu register groups" , size );
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}
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/* s2cr->type == 0 means translation, so initialise explicitly */
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smmu -> s2crs = devm_kmalloc_array (smmu -> dev , size , sizeof (* smmu -> s2crs ),
@@ -2094,6 +2120,7 @@ static int arm_smmu_device_probe(struct platform_device *pdev)
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iommu_register_instance (dev -> fwnode , & arm_smmu_ops );
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platform_set_drvdata (pdev , smmu );
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arm_smmu_device_reset (smmu );
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+ arm_smmu_test_smr_masks (smmu );
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/* Oh, for a proper bus abstraction */
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if (!iommu_present (& platform_bus_type ))
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