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sandy-huangrkhuangtao
sandy-huang
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rkhuangtao
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drm/rockchip: vop3: move cluster mix config from vop_ctrl to cluster_regs
cluster mix config followed cluster, so we move mix regsiter from vop_ctrl to cluster_regs is more suitable. Signed-off-by: Sandy Huang <[email protected]> Change-Id: I28d80ce9e902992870b9876296af3daa2f5add65
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-29
lines changed

4 files changed

+44
-29
lines changed

‎drivers/gpu/drm/rockchip/rockchip_drm_vop.h‎

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -552,6 +552,11 @@ struct vop2_cluster_regs {
552552
struct vop_reg enable;
553553
struct vop_reg afbc_enable;
554554
struct vop_reg lb_mode;
555+
556+
struct vop_reg src_color_ctrl;
557+
struct vop_reg dst_color_ctrl;
558+
struct vop_reg src_alpha_ctrl;
559+
struct vop_reg dst_alpha_ctrl;
555560
};
556561

557562
struct vop2_scl_regs {
@@ -1037,10 +1042,6 @@ struct vop2_ctrl {
10371042
struct vop_reg mipi0_ds_mode;
10381043
struct vop_reg mipi1_ds_mode;
10391044

1040-
struct vop_reg cluster0_src_color_ctrl;
1041-
struct vop_reg cluster0_dst_color_ctrl;
1042-
struct vop_reg cluster0_src_alpha_ctrl;
1043-
struct vop_reg cluster0_dst_alpha_ctrl;
10441045
struct vop_reg src_color_ctrl;
10451046
struct vop_reg dst_color_ctrl;
10461047
struct vop_reg src_alpha_ctrl;

‎drivers/gpu/drm/rockchip/rockchip_drm_vop2.c‎

Lines changed: 8 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -6992,11 +6992,10 @@ static int vop2_find_start_mixer_id_for_vp(struct vop2 *vop2, uint8_t port_id)
69926992
*/
69936993
static void vop2_setup_cluster_alpha(struct vop2 *vop2, struct vop2_cluster *cluster)
69946994
{
6995-
uint32_t src_color_ctrl_offset = vop2->data->ctrl->cluster0_src_color_ctrl.offset;
6996-
uint32_t dst_color_ctrl_offset = vop2->data->ctrl->cluster0_dst_color_ctrl.offset;
6997-
uint32_t src_alpha_ctrl_offset = vop2->data->ctrl->cluster0_src_alpha_ctrl.offset;
6998-
uint32_t dst_alpha_ctrl_offset = vop2->data->ctrl->cluster0_dst_alpha_ctrl.offset;
6999-
uint32_t offset = (cluster->main->phys_id * 0x10);
6995+
uint32_t src_color_ctrl_offset = cluster->main->regs->cluster->src_color_ctrl.offset;
6996+
uint32_t dst_color_ctrl_offset = cluster->main->regs->cluster->dst_color_ctrl.offset;
6997+
uint32_t src_alpha_ctrl_offset = cluster->main->regs->cluster->src_alpha_ctrl.offset;
6998+
uint32_t dst_alpha_ctrl_offset = cluster->main->regs->cluster->dst_alpha_ctrl.offset;
70006999
struct drm_framebuffer *fb;
70017000
struct vop2_alpha_config alpha_config;
70027001
struct vop2_alpha alpha;
@@ -7012,11 +7011,6 @@ static void vop2_setup_cluster_alpha(struct vop2 *vop2, struct vop2_cluster *clu
70127011
bool premulti_en = false;
70137012
bool swap = false;
70147013

7015-
if (cluster->main->phys_id == ROCKCHIP_VOP2_CLUSTER2)
7016-
offset = 0x20;
7017-
else if (cluster->main->phys_id == ROCKCHIP_VOP2_CLUSTER3)
7018-
offset = 0x30;
7019-
70207014
if (!sub_win) {
70217015
/* At one win mode, win0 is dst/bottom win, and win1 is a all zero src/top win */
70227016

@@ -7072,10 +7066,10 @@ static void vop2_setup_cluster_alpha(struct vop2 *vop2, struct vop2_cluster *clu
70727066
vop2_parse_alpha(&alpha_config, &alpha);
70737067

70747068
alpha.src_color_ctrl.bits.src_dst_swap = swap;
7075-
vop2_writel(vop2, src_color_ctrl_offset + offset, alpha.src_color_ctrl.val);
7076-
vop2_writel(vop2, dst_color_ctrl_offset + offset, alpha.dst_color_ctrl.val);
7077-
vop2_writel(vop2, src_alpha_ctrl_offset + offset, alpha.src_alpha_ctrl.val);
7078-
vop2_writel(vop2, dst_alpha_ctrl_offset + offset, alpha.dst_alpha_ctrl.val);
7069+
vop2_writel(vop2, src_color_ctrl_offset, alpha.src_color_ctrl.val);
7070+
vop2_writel(vop2, dst_color_ctrl_offset, alpha.dst_color_ctrl.val);
7071+
vop2_writel(vop2, src_alpha_ctrl_offset, alpha.src_alpha_ctrl.val);
7072+
vop2_writel(vop2, dst_alpha_ctrl_offset, alpha.dst_alpha_ctrl.val);
70797073
}
70807074

70817075
static void vop2_setup_alpha(struct vop2_video_port *vp,

‎drivers/gpu/drm/rockchip/rockchip_vop2_reg.c‎

Lines changed: 19 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1445,28 +1445,44 @@ static const struct vop2_layer_data rk3568_vop_layers[] = {
14451445

14461446
};
14471447

1448-
static const struct vop2_cluster_regs rk3568_vop_cluster0 = {
1448+
static const struct vop2_cluster_regs rk3568_vop_cluster0 = {
14491449
.afbc_enable = VOP_REG(RK3568_CLUSTER0_CTRL, 0x1, 1),
14501450
.enable = VOP_REG(RK3568_CLUSTER0_CTRL, 1, 0),
14511451
.lb_mode = VOP_REG(RK3568_CLUSTER0_CTRL, 0xf, 4),
1452+
.src_color_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL, 0xffffffff, 0),
1453+
.dst_color_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_DST_COLOR_CTRL, 0xffffffff, 0),
1454+
.src_alpha_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL, 0xffffffff, 0),
1455+
.dst_alpha_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL, 0xffffffff, 0),
14521456
};
14531457

1454-
static const struct vop2_cluster_regs rk3568_vop_cluster1 = {
1458+
static const struct vop2_cluster_regs rk3568_vop_cluster1 = {
14551459
.afbc_enable = VOP_REG(RK3568_CLUSTER1_CTRL, 0x1, 1),
14561460
.enable = VOP_REG(RK3568_CLUSTER1_CTRL, 1, 0),
14571461
.lb_mode = VOP_REG(RK3568_CLUSTER1_CTRL, 0xf, 4),
1462+
.src_color_ctrl = VOP_REG(RK3568_CLUSTER1_MIX_SRC_COLOR_CTRL, 0xffffffff, 0),
1463+
.dst_color_ctrl = VOP_REG(RK3568_CLUSTER1_MIX_DST_COLOR_CTRL, 0xffffffff, 0),
1464+
.src_alpha_ctrl = VOP_REG(RK3568_CLUSTER1_MIX_SRC_ALPHA_CTRL, 0xffffffff, 0),
1465+
.dst_alpha_ctrl = VOP_REG(RK3568_CLUSTER1_MIX_DST_ALPHA_CTRL, 0xffffffff, 0),
14581466
};
14591467

1460-
static const struct vop2_cluster_regs rk3588_vop_cluster2 = {
1468+
static const struct vop2_cluster_regs rk3588_vop_cluster2 = {
14611469
.afbc_enable = VOP_REG(RK3588_CLUSTER2_CTRL, 0x1, 1),
14621470
.enable = VOP_REG(RK3588_CLUSTER2_CTRL, 1, 0),
14631471
.lb_mode = VOP_REG(RK3588_CLUSTER2_CTRL, 0xf, 4),
1472+
.src_color_ctrl = VOP_REG(RK3588_CLUSTER2_MIX_SRC_COLOR_CTRL, 0xffffffff, 0),
1473+
.dst_color_ctrl = VOP_REG(RK3588_CLUSTER2_MIX_DST_COLOR_CTRL, 0xffffffff, 0),
1474+
.src_alpha_ctrl = VOP_REG(RK3588_CLUSTER2_MIX_SRC_ALPHA_CTRL, 0xffffffff, 0),
1475+
.dst_alpha_ctrl = VOP_REG(RK3588_CLUSTER2_MIX_DST_ALPHA_CTRL, 0xffffffff, 0),
14641476
};
14651477

14661478
static const struct vop2_cluster_regs rk3588_vop_cluster3 = {
14671479
.afbc_enable = VOP_REG(RK3588_CLUSTER3_CTRL, 0x1, 1),
14681480
.enable = VOP_REG(RK3588_CLUSTER3_CTRL, 1, 0),
14691481
.lb_mode = VOP_REG(RK3588_CLUSTER3_CTRL, 0xf, 4),
1482+
.src_color_ctrl = VOP_REG(RK3588_CLUSTER3_MIX_SRC_COLOR_CTRL, 0xffffffff, 0),
1483+
.dst_color_ctrl = VOP_REG(RK3588_CLUSTER3_MIX_DST_COLOR_CTRL, 0xffffffff, 0),
1484+
.src_alpha_ctrl = VOP_REG(RK3588_CLUSTER3_MIX_SRC_ALPHA_CTRL, 0xffffffff, 0),
1485+
.dst_alpha_ctrl = VOP_REG(RK3588_CLUSTER3_MIX_DST_ALPHA_CTRL, 0xffffffff, 0),
14701486
};
14711487

14721488
static const struct vop_afbc rk3568_cluster0_afbc = {
@@ -2584,10 +2600,6 @@ static const struct vop2_ctrl rk3568_vop_ctrl = {
25842600
.if_ctrl_cfg_done_imd = VOP_REG(RK3568_DSP_IF_POL, 0x1, 28),
25852601
.version = VOP_REG(RK3568_VERSION_INFO, 0xffff, 16),
25862602
.lut_dma_en = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0x1, 0),
2587-
.cluster0_src_color_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL, 0xffffffff, 0),
2588-
.cluster0_dst_color_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_DST_COLOR_CTRL, 0xffffffff, 0),
2589-
.cluster0_src_alpha_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL, 0xffffffff, 0),
2590-
.cluster0_dst_alpha_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL, 0xffffffff, 0),
25912603
.src_color_ctrl = VOP_REG(RK3568_MIX0_SRC_COLOR_CTRL, 0xffffffff, 0),
25922604
.dst_color_ctrl = VOP_REG(RK3568_MIX0_DST_COLOR_CTRL, 0xffffffff, 0),
25932605
.src_alpha_ctrl = VOP_REG(RK3568_MIX0_SRC_ALPHA_CTRL, 0xffffffff, 0),
@@ -2667,10 +2679,6 @@ static const struct vop2_ctrl rk3588_vop_ctrl = {
26672679
.if_ctrl_cfg_done_imd = VOP_REG(RK3568_DSP_IF_POL, 0x1, 28),
26682680
.version = VOP_REG(RK3568_VERSION_INFO, 0xffff, 16),
26692681
.lut_dma_en = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0x1, 0),
2670-
.cluster0_src_color_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL, 0xffffffff, 0),
2671-
.cluster0_dst_color_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_DST_COLOR_CTRL, 0xffffffff, 0),
2672-
.cluster0_src_alpha_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL, 0xffffffff, 0),
2673-
.cluster0_dst_alpha_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL, 0xffffffff, 0),
26742682
.src_color_ctrl = VOP_REG(RK3568_MIX0_SRC_COLOR_CTRL, 0xffffffff, 0),
26752683
.dst_color_ctrl = VOP_REG(RK3568_MIX0_DST_COLOR_CTRL, 0xffffffff, 0),
26762684
.src_alpha_ctrl = VOP_REG(RK3568_MIX0_SRC_ALPHA_CTRL, 0xffffffff, 0),

‎drivers/gpu/drm/rockchip/rockchip_vop_reg.h‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1217,6 +1217,18 @@
12171217
#define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL 0x614
12181218
#define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x618
12191219
#define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL 0x61C
1220+
#define RK3568_CLUSTER1_MIX_SRC_COLOR_CTRL 0x620
1221+
#define RK3568_CLUSTER1_MIX_DST_COLOR_CTRL 0x624
1222+
#define RK3568_CLUSTER1_MIX_SRC_ALPHA_CTRL 0x628
1223+
#define RK3568_CLUSTER1_MIX_DST_ALPHA_CTRL 0x62C
1224+
#define RK3588_CLUSTER2_MIX_SRC_COLOR_CTRL 0x630
1225+
#define RK3588_CLUSTER2_MIX_DST_COLOR_CTRL 0x634
1226+
#define RK3588_CLUSTER2_MIX_SRC_ALPHA_CTRL 0x638
1227+
#define RK3588_CLUSTER2_MIX_DST_ALPHA_CTRL 0x63C
1228+
#define RK3588_CLUSTER3_MIX_SRC_COLOR_CTRL 0x640
1229+
#define RK3588_CLUSTER3_MIX_DST_COLOR_CTRL 0x644
1230+
#define RK3588_CLUSTER3_MIX_SRC_ALPHA_CTRL 0x648
1231+
#define RK3588_CLUSTER3_MIX_DST_ALPHA_CTRL 0x64C
12201232
#define RK3568_MIX0_SRC_COLOR_CTRL 0x650
12211233
#define RK3568_MIX0_DST_COLOR_CTRL 0x654
12221234
#define RK3568_MIX0_SRC_ALPHA_CTRL 0x658

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