Initial commit

Author: koderchina

src/controlUnit.v

@@ -0,0 +1,104 @@
+module controlUnit(
+    // Signal kojim vanjski svijet dojavljuje da je spremna nova ul. znacajka
+    input wire clk,
+    input wire rst_n,
+    input wire dataw_rdy, 
+    output wire [3:0] oe_reg;
+    output wire [3:0] we_reg;
+);
+
+// Counter for adressing the current line buffer being written to
+reg [1:0] current_write_buff;
+// Counts total number of lines loaded
+reg [9:0] line_cnt; 
+// Counter for the number of input features
+reg [2:0] write_feature_cnt;
+
+// Counter for multiplexing line buffer output enable ports
+reg [1:0] current_read_buff;
+// Read ready signal
+wire datar_rdy;
+// Counter for number of read features
+reg [2:0] read_feature_cnt;
+
+// ============ write controller ============
+always @(posedge clk)
+begin
+    if (!rst_n)
+        write_feature_cnt <= 3'b0;
+    else if (dataw_rdy)
+        write_feature_cnt <= write_feature_cnt + 1;
+end
+
+always @(posedge clk)
+begin
+    if (!rst_n)
+    begin
+        current_write_buff <= 2'b0;
+        line_cnt <= 10'b0;
+    end
+    else if (write_feature_cnt == 7 & dataw_rdy)
+    begin
+        current_write_buff <= current_write_buff + 1;
+        line_cnt <= line_cnt + 1;
+    end
+end
+
+// Combo logic for write enable activation
+always @(*)
+begin
+    we_reg = 3'b0;
+    we_reg[current_write_buff] = 1;
+end
+// ============ end write controller ============
+
+// ============ read controller =============
+always @(posedge clk)
+begin
+    if (!rst_n)
+        read_feature_cnt <= 3'b0;
+    else if (datar_rdy)
+        read_feature_cnt <= read_feature_cnt + 1;
+end
+
+always @(posedge clk)
+begin
+    if (!rst_n)
+        current_read_buff <= 2'b0;
+    else if (read_feature_cnt == 7 & datar_rdy)
+        current_read_buff <= current_read_buff + 1;
+end
+
+// Combo logic for read enable activation
+always @(*)
+begin
+    case (current_read_buff)
+        0: begin
+            oe_reg[0] = datar_rdy;
+            oe_reg[1] = datar_rdy;
+            oe_reg[2] = datar_rdy;
+            oe_reg[3] = 1'b0;
+        end
+        1: begin
+            oe_reg[0] = 1'b0;
+            oe_reg[1] = datar_rdy;
+            oe_reg[2] = datar_rdy;
+            oe_reg[3] = datar_rdy;
+        end
+        2: begin
+            oe_reg[0] = datar_rdy;
+            oe_reg[1] = 1'b0;
+            oe_reg[2] = datar_rdy;
+            oe_reg[3] = datar_rdy;
+        end
+        3: begin
+            oe_reg[0] = datar_rdy;
+            oe_reg[1] = datar_rdy;
+            oe_reg[2] = 1'b0;
+            oe_reg[3] = datar_rdy;
+        end
+    endcase 
+end
+// ============ end read controller =============
+
+endmodule

src/lineBuffer.v

@@ -0,0 +1,55 @@
+module lineBuffer(
+    input wire clk,
+    input wire rst_n, // low to reset
+    input wire we, // write enable
+    input wire oe, // output enable
+    input wire [7:0] wr_data,
+    output wire [23:0] rd_data // output data consists of three consecutive values stored in memory
+);
+
+// line buffer with eight 8-bit locations
+reg [7:0] buffer [7:0];
+
+// counter register for writing
+reg [2:0] w_ptr; // 0-7 
+
+// counter register for reading
+reg [2:0] r_ptr; // 0-7
+
+/*
+line buffer modeled like single-port RAM:
+https://yosyshq.readthedocs.io/projects/yosys/en/latest/using_yosys/synthesis/memory.html#single-port-ram-memory-patterns
+*/
+// write logic
+always @(posedge clk)
+begin
+    if (we)
+        buffer[w_ptr] <= wr_data;
+end
+
+// read logic
+assign rd_data = {buffer[rd_data], buffer[rd_data + 1], buffer[rd_data + 2]};
+
+// write counter logic
+always @(posedge clk)
+begin
+    if (!rst_n)
+        w_ptr <= 3'b0;
+    else if (we)
+        w_ptr <= w_ptr + 1'b1;
+    else
+        w_ptr <= w_ptr; // done to prevent a latch from inferring
+end
+
+// read counter logic
+always @(posedge clk)
+begin
+    if (!rst_n)
+        r_ptr <= 3'b0;
+    else if (oe)
+        r_ptr <= r_ptr + 1'b1;
+    else
+        r_ptr <= r_ptr; // done to prevent a latch from inferring
+end
+
+endmodule

src/project.v

@@ -5,7 +5,7 @@
 
 `default_nettype none
 
-module tt_um_example (
+module tt_um_koderchina_conv (
     input  wire [7:0] ui_in,    // Dedicated inputs
     output wire [7:0] uo_out,   // Dedicated outputs
     input  wire [7:0] uio_in,   // IOs: Input path
@@ -17,9 +17,49 @@ module tt_um_example (
 );
 
   // All output pins must be assigned. If not used, assign to 0.
-  assign uo_out  = ui_in + uio_in;  // Example: ou_out is the sum of ui_in and uio_in
-  assign uio_out = 0;
-  assign uio_oe  = 0;
+  wire we = ui_in[0];       // use bit 0 as write enable
+  wire oe = ui_in[1];       // use bit 1 as output enable
+  wire [7:0] wr_data = ui_in[7:0]; // could use all 8 input bits as data
+  assign uio_oe  = 8'hFF;  // all uio pins drive outputs
+
+  wire[3:0] we_reg;
+  wire[3:0] oe_reg;
+
+  lineBuffer b0(
+    .clk(clk),
+    .rst_n(rst_n),
+    .we(we_reg[0]),
+    .oe(oe_reg[0]),
+    .wr_data(data_in),
+    .rd_data()
+  );
+
+  lineBuffer b1(
+      .clk(clk),
+      .rst_n(rst_n),
+      .we(we_reg[1]),
+      .oe(oe_reg[1]),
+      .wr_data(data_in),
+      .rd_data()
+  );
+
+  lineBuffer b2(
+      .clk(clk),
+      .rst_n(rst_n),
+      .we(we_reg[2]),
+      .oe(oe_reg[2]),
+      .wr_data(data_in),
+      .rd_data()
+  );
+
+  lineBuffer b3(
+      .clk(clk),
+      .rst_n(rst_n),
+      .we(we_reg[3]),
+      .oe(oe_reg[3]),
+      .wr_data(data_in),
+      .rd_data()
+  );
 
   // List all unused inputs to prevent warnings
   wire _unused = &{ena, clk, rst_n, 1'b0};