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[AMDGPU] gfx1251 VOP2 dpp support (llvm#159641)
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‎llvm/lib/Target/AMDGPU/VOP2Instructions.td‎

Lines changed: 45 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -287,10 +287,14 @@ multiclass VOP2bInst <string opName,
287287
def _e64 : VOP3InstBase <opName, P, node, 1>,
288288
Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;
289289

290-
let SubtargetPredicate = isGFX11Plus in {
291-
if P.HasExtVOP3DPP then
292-
def _e64_dpp : VOP3_DPP_Pseudo <opName, P>;
293-
} // End SubtargetPredicate = isGFX11Plus
290+
if P.HasExtVOP3DPP then
291+
def _e64_dpp : VOP3_DPP_Pseudo <opName, P> {
292+
let SubtargetPredicate = isGFX11Plus;
293+
}
294+
else if P.HasExt64BitDPP then
295+
def _e64_dpp : VOP3_DPP_Pseudo <opName, P> {
296+
let OtherPredicates = [HasDPALU_DPP];
297+
}
294298
}
295299
}
296300

@@ -345,10 +349,14 @@ multiclass
345349
VOPD_Component<VOPDOp, VOPDName>;
346350
}
347351

348-
let SubtargetPredicate = isGFX11Plus in {
349-
if P.HasExtVOP3DPP then
350-
def _e64_dpp : VOP3_DPP_Pseudo <opName, P>;
351-
} // End SubtargetPredicate = isGFX11Plus
352+
if P.HasExtVOP3DPP then
353+
def _e64_dpp : VOP3_DPP_Pseudo <opName, P> {
354+
let SubtargetPredicate = isGFX11Plus;
355+
}
356+
else if P.HasExt64BitDPP then
357+
def _e64_dpp : VOP3_DPP_Pseudo <opName, P> {
358+
let OtherPredicates = [HasDPALU_DPP];
359+
}
352360
}
353361
}
354362

@@ -1607,8 +1615,9 @@ multiclass VOP2_Real_dpp<GFXGen Gen, bits<6> op> {
16071615
}
16081616

16091617
multiclass VOP2_Real_dpp8<GFXGen Gen, bits<6> op> {
1610-
if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP then
1611-
def _dpp8#Gen.Suffix : VOP2_DPP8_Gen<op, !cast<VOP2_Pseudo>(NAME#"_e32"), Gen>;
1618+
defvar ps = !cast<VOP2_Pseudo>(NAME#"_e32");
1619+
if !and(ps.Pfl.HasExtDPP, !not(ps.Pfl.HasExt64BitDPP)) then
1620+
def _dpp8#Gen.Suffix : VOP2_DPP8_Gen<op, ps, Gen>;
16121621
}
16131622

16141623
//===------------------------- VOP2 (with name) -------------------------===//
@@ -1643,10 +1652,10 @@ multiclass VOP2_Real_dpp_with_name<GFXGen Gen, bits<6> op, string opName,
16431652
multiclass VOP2_Real_dpp8_with_name<GFXGen Gen, bits<6> op, string opName,
16441653
string asmName> {
16451654
defvar ps = !cast<VOP2_Pseudo>(opName#"_e32");
1646-
if ps.Pfl.HasExtDPP then
1647-
def _dpp8#Gen.Suffix : VOP2_DPP8_Gen<op, ps, Gen> {
1648-
let AsmString = asmName # ps.Pfl.AsmDPP8;
1649-
}
1655+
if !and(ps.Pfl.HasExtDPP, !not(ps.Pfl.HasExt64BitDPP)) then
1656+
def _dpp8#Gen.Suffix : VOP2_DPP8_Gen<op, ps, Gen> {
1657+
let AsmString = asmName # ps.Pfl.AsmDPP8;
1658+
}
16501659
}
16511660

16521661
//===------------------------------ VOP2be ------------------------------===//
@@ -1687,32 +1696,32 @@ multiclass VOP2be_Real_dpp<GFXGen Gen, bits<6> op, string opName, string asmName
16871696
}
16881697
}
16891698
multiclass VOP2be_Real_dpp8<GFXGen Gen, bits<6> op, string opName, string asmName> {
1690-
if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP then
1699+
defvar ps = !cast<VOP2_Pseudo>(opName#"_e32");
1700+
if !and(ps.Pfl.HasExtDPP, !not(ps.Pfl.HasExt64BitDPP)) then {
16911701
def _dpp8#Gen.Suffix :
1692-
VOP2_DPP8_Gen<op, !cast<VOP2_Pseudo>(opName#"_e32"), Gen> {
1693-
string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
1702+
VOP2_DPP8_Gen<op, ps, Gen> {
1703+
string AsmDPP8 = ps.Pfl.AsmDPP8;
16941704
let AsmString = asmName # !subst(", vcc", "", AsmDPP8);
16951705
}
1696-
if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP then
16971706
def _dpp8_w32#Gen.Suffix :
1698-
VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> {
1699-
string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
1707+
VOP2_DPP8<op, ps> {
1708+
string AsmDPP8 = ps.Pfl.AsmDPP8;
17001709
let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP8);
17011710
let isAsmParserOnly = 1;
17021711
let WaveSizePredicate = isWave32;
17031712
let AssemblerPredicate = Gen.AssemblerPredicate;
17041713
let DecoderNamespace = Gen.DecoderNamespace;
17051714
}
1706-
if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP then
17071715
def _dpp8_w64#Gen.Suffix :
1708-
VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> {
1709-
string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
1716+
VOP2_DPP8<op, ps> {
1717+
string AsmDPP8 = ps.Pfl.AsmDPP8;
17101718
let AsmString = asmName # AsmDPP8;
17111719
let isAsmParserOnly = 1;
17121720
let WaveSizePredicate = isWave64;
17131721
let AssemblerPredicate = Gen.AssemblerPredicate;
17141722
let DecoderNamespace = Gen.DecoderNamespace;
17151723
}
1724+
}
17161725
}
17171726

17181727
// We don't want to override separate decoderNamespaces within these
@@ -1777,9 +1786,11 @@ multiclass VOP2_Real_NO_DPP_with_name<GFXGen Gen, bits<6> op, string opName,
17771786
}
17781787
}
17791788

1780-
multiclass VOP2_Real_NO_DPP_with_alias<GFXGen Gen, bits<6> op, string alias> {
1789+
multiclass VOP2_Real_with_DPP16_with_alias<GFXGen Gen, bits<6> op, string alias> {
17811790
defm NAME : VOP2_Real_e32<Gen, op>,
1782-
VOP2_Real_e64<Gen, op>;
1791+
VOP2_Real_dpp<Gen, op>,
1792+
VOP2_Real_e64<Gen, op>,
1793+
VOP3_Real_dpp_Base<Gen, {0, 1, 0, 0, op{5-0}}>;
17831794
def Gen.Suffix#"_alias" : AMDGPUMnemonicAlias<alias, NAME> {
17841795
let AssemblerPredicate = Gen.AssemblerPredicate;
17851796
}
@@ -1808,6 +1819,9 @@ multiclass VOP2_Real_FULL_t16_gfx12<bits<6> op, string opName,
18081819
}
18091820
}
18101821

1822+
multiclass VOP2_Real_with_DPP16_with_alias_gfx12<bits<6> op, string alias> :
1823+
VOP2_Real_with_DPP16_with_alias<GFX12Gen, op, alias>;
1824+
18111825
multiclass VOP2_Real_FULL_t16_and_fake16_gfx12<bits<6> op, string opName,
18121826
string asmName, string alias> {
18131827
defm _t16: VOP2_Real_FULL_t16_gfx12<op, opName#"_t16", asmName, alias>;
@@ -1818,14 +1832,11 @@ multiclass VOP2_Real_NO_DPP_with_name_gfx12<bits<6> op, string opName,
18181832
string asmName> :
18191833
VOP2_Real_NO_DPP_with_name<GFX12Gen, op, opName, asmName>;
18201834

1821-
multiclass VOP2_Real_NO_DPP_with_alias_gfx12<bits<6> op, string alias> :
1822-
VOP2_Real_NO_DPP_with_alias<GFX12Gen, op, alias>;
1823-
1824-
defm V_ADD_F64 : VOP2_Real_NO_DPP_with_name_gfx12<0x002, "V_ADD_F64_pseudo", "v_add_f64">;
1825-
defm V_MUL_F64 : VOP2_Real_NO_DPP_with_name_gfx12<0x006, "V_MUL_F64_pseudo", "v_mul_f64">;
1826-
defm V_LSHLREV_B64 : VOP2_Real_NO_DPP_with_name_gfx12<0x01f, "V_LSHLREV_B64_pseudo", "v_lshlrev_b64">;
1827-
defm V_MIN_NUM_F64 : VOP2_Real_NO_DPP_with_alias_gfx12<0x00d, "v_min_f64">;
1828-
defm V_MAX_NUM_F64 : VOP2_Real_NO_DPP_with_alias_gfx12<0x00e, "v_max_f64">;
1835+
defm V_ADD_F64 : VOP2_Real_FULL_with_name_gfx12<0x002, "V_ADD_F64_pseudo", "v_add_f64">;
1836+
defm V_MUL_F64 : VOP2_Real_FULL_with_name_gfx12<0x006, "V_MUL_F64_pseudo", "v_mul_f64">;
1837+
defm V_LSHLREV_B64 : VOP2_Real_FULL_with_name_gfx12<0x01f, "V_LSHLREV_B64_pseudo", "v_lshlrev_b64">;
1838+
defm V_MIN_NUM_F64 : VOP2_Real_with_DPP16_with_alias_gfx12<0x00d, "v_min_f64">;
1839+
defm V_MAX_NUM_F64 : VOP2_Real_with_DPP16_with_alias_gfx12<0x00e, "v_max_f64">;
18291840

18301841
defm V_CNDMASK_B32 : VOP2e_Real_gfx12<0x001, "V_CNDMASK_B32", "v_cndmask_b32">;
18311842
defm V_ADD_CO_CI_U32 :
@@ -2776,7 +2787,7 @@ let DecoderNamespace = "GFX90A" in {
27762787
}
27772788
} // End AssemblerPredicate = isGFX90APlus, DecoderNamespace = "GFX90A"
27782789

2779-
let SubtargetPredicate = HasFmacF64Inst in {
2790+
let SubtargetPredicate = HasFmacF64Inst, OtherPredicates = [isGFX9Only] in {
27802791
defm V_FMAC_F64 : VOP2_Real_e32e64_gfx90a <0x4>;
27812792
} // End SubtargetPredicate = HasFmacF64Inst
27822793

‎llvm/test/CodeGen/AMDGPU/dpp_combine.ll‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,8 @@
44
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck %s -check-prefixes=GCN,GFX11-FAKE16
55
; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -mattr=+real-true16 < %s | FileCheck %s -check-prefixes=GCN,GFX11-TRUE16
66
; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -mattr=-real-true16 < %s | FileCheck %s -check-prefixes=GCN,GFX11-FAKE16
7+
; RUN: llc -mtriple=amdgcn -mcpu=gfx1251 -mattr=+real-true16 < %s | FileCheck %s -check-prefixes=GCN,GFX11-TRUE16
8+
; RUN: llc -mtriple=amdgcn -mcpu=gfx1251 -mattr=-real-true16 < %s | FileCheck %s -check-prefixes=GCN,GFX11-FAKE16
79

810
; GCN-LABEL: {{^}}dpp_add:
911
; GCN: global_load_{{dword|b32}} [[V:v[0-9]+]],
@@ -49,7 +51,9 @@ define amdgpu_kernel void @dpp_fadd(ptr addrspace(1) %arg) {
4951
ret void
5052
}
5153

52-
; Fails to combine because v_mul_lo_u32 has no e32 or dpp form.
54+
; Fails to combine prior to gfx1251 because v_mul_lo_u32 has no e32 or dpp form.
55+
; Fails to combine on gfx1251 because DPP control value is invalid for DP DPP and v_mul_lo_u32 is
56+
; classified as DP DPP.
5357
; GCN-LABEL: {{^}}dpp_mul:
5458
; GCN: global_load_{{dword|b32}} [[V:v[0-9]+]],
5559
; GCN: v_mov_b32_e32 [[V2:v[0-9]+]], [[V]]

‎llvm/test/MC/AMDGPU/gfx1251_asm_vop2_dpp16.s‎

Lines changed: 74 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,74 @@
1+
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1251 -show-encoding < %s | FileCheck --check-prefix=GFX1251 %s
2+
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1250 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX1250-ERR --implicit-check-not=error: --strict-whitespace %s
3+
4+
v_add_nc_u64 v[4:5], v[2:3], v[4:5] row_share:3 row_mask:0x3 bank_mask:0x0 fi:1
5+
// GFX1251: v_add_nc_u64_dpp v[4:5], v[2:3], v[4:5] row_share:3 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0x08,0x08,0x50,0x02,0x53,0x05,0x30]
6+
// GFX1250-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: not a valid operand.
7+
// GFX1250-ERR-NEXT:{{^}}v_add_nc_u64 v[4:5], v[2:3], v[4:5] row_share:3 row_mask:0x3 bank_mask:0x0 fi:1
8+
// GFX1250-ERR-NEXT:{{^}} ^
9+
10+
v_add_nc_u64 v[4:5], v[2:3], v[4:5] row_share:0 row_mask:0xf bank_mask:0xf
11+
// GFX1251: v_add_nc_u64_dpp v[4:5], v[2:3], v[4:5] row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x08,0x08,0x50,0x02,0x50,0x01,0xff]
12+
// GFX1250-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: not a valid operand.
13+
// GFX1250-ERR-NEXT:{{^}}v_add_nc_u64 v[4:5], v[2:3], v[4:5] row_share:0 row_mask:0xf bank_mask:0xf
14+
// GFX1250-ERR-NEXT:{{^}} ^
15+
16+
v_add_nc_u64 v[4:5], v[2:3], v[4:5] row_share:15 row_mask:0x0 bank_mask:0x1
17+
// GFX1251: v_add_nc_u64_dpp v[4:5], v[2:3], v[4:5] row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x08,0x08,0x50,0x02,0x5f,0x01,0x01]
18+
// GFX1250-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: not a valid operand.
19+
// GFX1250-ERR-NEXT:{{^}}v_add_nc_u64 v[4:5], v[2:3], v[4:5] row_share:15 row_mask:0x0 bank_mask:0x1
20+
// GFX1250-ERR-NEXT:{{^}} ^
21+
22+
v_sub_nc_u64 v[4:5], v[2:3], v[4:5] row_share:3 row_mask:0x3 bank_mask:0x0 fi:1
23+
// GFX1251: v_sub_nc_u64_dpp v[4:5], v[2:3], v[4:5] row_share:3 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0x08,0x08,0x52,0x02,0x53,0x05,0x30]
24+
// GFX1250-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: not a valid operand.
25+
// GFX1250-ERR-NEXT:{{^}}v_sub_nc_u64 v[4:5], v[2:3], v[4:5] row_share:3 row_mask:0x3 bank_mask:0x0 fi:1
26+
// GFX1250-ERR-NEXT:{{^}} ^
27+
28+
v_sub_nc_u64 v[4:5], v[2:3], v[4:5] row_share:0 row_mask:0xf bank_mask:0xf
29+
// GFX1251: v_sub_nc_u64_dpp v[4:5], v[2:3], v[4:5] row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x08,0x08,0x52,0x02,0x50,0x01,0xff]
30+
// GFX1250-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: not a valid operand.
31+
// GFX1250-ERR-NEXT:{{^}}v_sub_nc_u64 v[4:5], v[2:3], v[4:5] row_share:0 row_mask:0xf bank_mask:0xf
32+
// GFX1250-ERR-NEXT:{{^}} ^
33+
34+
v_sub_nc_u64 v[4:5], v[2:3], v[4:5] row_share:15 row_mask:0x0 bank_mask:0x1
35+
// GFX1251: v_sub_nc_u64_dpp v[4:5], v[2:3], v[4:5] row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x08,0x08,0x52,0x02,0x5f,0x01,0x01]
36+
// GFX1250-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: not a valid operand.
37+
// GFX1250-ERR-NEXT:{{^}}v_sub_nc_u64 v[4:5], v[2:3], v[4:5] row_share:15 row_mask:0x0 bank_mask:0x1
38+
// GFX1250-ERR-NEXT:{{^}} ^
39+
40+
v_fmac_f64 v[4:5], v[2:3], v[4:5] row_share:1
41+
// GFX1251: v_fmac_f64_dpp v[4:5], v[2:3], v[4:5] row_share:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x08,0x08,0x2e,0x02,0x51,0x01,0xff]
42+
// GFX1250-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: not a valid operand.
43+
// GFX1250-ERR-NEXT:{{^}}v_fmac_f64 v[4:5], v[2:3], v[4:5] row_share:1
44+
// GFX1250-ERR-NEXT:{{^}} ^
45+
46+
v_add_f64 v[4:5], v[2:3], v[4:5] row_share:1
47+
// GFX1251: v_add_f64_dpp v[4:5], v[2:3], v[4:5] row_share:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x08,0x08,0x04,0x02,0x51,0x01,0xff]
48+
// GFX1250-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: not a valid operand.
49+
// GFX1250-ERR-NEXT:{{^}}v_add_f64 v[4:5], v[2:3], v[4:5] row_share:1
50+
// GFX1250-ERR-NEXT:{{^}} ^
51+
52+
v_mul_f64 v[4:5], v[2:3], v[4:5] row_share:1
53+
// GFX1251: v_mul_f64_dpp v[4:5], v[2:3], v[4:5] row_share:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x08,0x08,0x0c,0x02,0x51,0x01,0xff]
54+
// GFX1250-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: not a valid operand.
55+
// GFX1250-ERR-NEXT:{{^}}v_mul_f64 v[4:5], v[2:3], v[4:5] row_share:1
56+
// GFX1250-ERR-NEXT:{{^}} ^
57+
58+
v_max_num_f64 v[4:5], v[2:3], v[4:5] row_share:1
59+
// GFX1251: v_max_num_f64_dpp v[4:5], v[2:3], v[4:5] row_share:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x08,0x08,0x1c,0x02,0x51,0x01,0xff]
60+
// GFX1250-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: not a valid operand.
61+
// GFX1250-ERR-NEXT:{{^}}v_max_num_f64 v[4:5], v[2:3], v[4:5] row_share:1
62+
// GFX1250-ERR-NEXT:{{^}} ^
63+
64+
v_min_num_f64 v[4:5], v[2:3], v[4:5] row_share:1
65+
// GFX1251: v_min_num_f64_dpp v[4:5], v[2:3], v[4:5] row_share:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x08,0x08,0x1a,0x02,0x51,0x01,0xff]
66+
// GFX1250-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: not a valid operand.
67+
// GFX1250-ERR-NEXT:{{^}}v_min_num_f64 v[4:5], v[2:3], v[4:5] row_share:1
68+
// GFX1250-ERR-NEXT:{{^}} ^
69+
70+
v_lshlrev_b64 v[4:5], v2, v[4:5] row_share:1
71+
// GFX1251: v_lshlrev_b64_dpp v[4:5], v2, v[4:5] row_share:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x08,0x08,0x3e,0x02,0x51,0x01,0xff]
72+
// GFX1250-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: not a valid operand.
73+
// GFX1250-ERR-NEXT:{{^}}v_lshlrev_b64 v[4:5], v2, v[4:5] row_share:1
74+
// GFX1250-ERR-NEXT:{{^}} ^

‎llvm/test/MC/AMDGPU/gfx1251_asm_vop2_err.s‎

Lines changed: 106 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,106 @@
1+
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1251 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX1251-ERR --implicit-check-not=error: --strict-whitespace %s
2+
3+
v_add_nc_u64 v[2:3], v[2:3], v[4:5] dpp8:[7,6,5,4,3,2,1,0]
4+
// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
5+
// GFX1251-ERR-NEXT:{{^}}v_add_nc_u64 v[2:3], v[2:3], v[4:5] dpp8:[7,6,5,4,3,2,1,0]
6+
// GFX1251-ERR-NEXT:{{^}} ^
7+
8+
v_sub_nc_u64 v[2:3], v[2:3], v[4:5] dpp8:[7,6,5,4,3,2,1,0]
9+
// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
10+
// GFX1251-ERR-NEXT:{{^}}v_sub_nc_u64 v[2:3], v[2:3], v[4:5] dpp8:[7,6,5,4,3,2,1,0]
11+
// GFX1251-ERR-NEXT:{{^}} ^
12+
13+
v_fmac_f64 v[4:5], v[2:3], v[4:5] dpp8:[7,6,5,4,3,2,1,0]
14+
// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
15+
// GFX1251-ERR-NEXT:{{^}}v_fmac_f64 v[4:5], v[2:3], v[4:5] dpp8:[7,6,5,4,3,2,1,0]
16+
// GFX1251-ERR-NEXT:{{^}} ^
17+
18+
v_add_f64 v[4:5], v[2:3], v[4:5] dpp8:[7,6,5,4,3,2,1,0]
19+
// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
20+
// GFX1251-ERR-NEXT:{{^}}v_add_f64 v[4:5], v[2:3], v[4:5] dpp8:[7,6,5,4,3,2,1,0]
21+
// GFX1251-ERR-NEXT:{{^}} ^
22+
23+
v_mul_f64 v[4:5], v[2:3], v[4:5] dpp8:[7,6,5,4,3,2,1,0]
24+
// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
25+
// GFX1251-ERR-NEXT:{{^}}v_mul_f64 v[4:5], v[2:3], v[4:5] dpp8:[7,6,5,4,3,2,1,0]
26+
// GFX1251-ERR-NEXT:{{^}} ^
27+
28+
v_max_num_f64 v[4:5], v[2:3], v[4:5] dpp8:[7,6,5,4,3,2,1,0]
29+
// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
30+
// GFX1251-ERR-NEXT:{{^}}v_max_num_f64 v[4:5], v[2:3], v[4:5] dpp8:[7,6,5,4,3,2,1,0]
31+
// GFX1251-ERR-NEXT:{{^}} ^
32+
33+
v_min_num_f64 v[4:5], v[2:3], v[4:5] dpp8:[7,6,5,4,3,2,1,0]
34+
// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
35+
// GFX1251-ERR-NEXT:{{^}}v_min_num_f64 v[4:5], v[2:3], v[4:5] dpp8:[7,6,5,4,3,2,1,0]
36+
// GFX1251-ERR-NEXT:{{^}} ^
37+
38+
v_lshlrev_b64 v[4:5], v2, v[4:5] dpp8:[7,6,5,4,3,2,1,0]
39+
// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
40+
// GFX1251-ERR-NEXT:{{^}}v_lshlrev_b64 v[4:5], v2, v[4:5] dpp8:[7,6,5,4,3,2,1,0]
41+
// GFX1251-ERR-NEXT:{{^}} ^
42+
43+
v_fmamk_f64 v[4:5], v[2:3], 123.0, v[6:7] dpp8:[7,6,5,4,3,2,1,0]
44+
// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
45+
// GFX1251-ERR-NEXT:{{^}}v_fmamk_f64 v[4:5], v[2:3], 123.0, v[6:7] dpp8:[7,6,5,4,3,2,1,0]
46+
// GFX1251-ERR-NEXT:{{^}} ^
47+
48+
v_fmaak_f64 v[4:5], v[2:3], v[6:7], 123.0 dpp8:[7,6,5,4,3,2,1,0]
49+
// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
50+
// GFX1251-ERR-NEXT:{{^}}v_fmaak_f64 v[4:5], v[2:3], v[6:7], 123.0 dpp8:[7,6,5,4,3,2,1,0]
51+
// GFX1251-ERR-NEXT:{{^}} ^
52+
53+
v_add_nc_u64 v[4:5], v[2:3], v[4:5] quad_perm:[3,2,1,0]
54+
// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: DP ALU dpp only supports row_share
55+
// GFX1251-ERR-NEXT:{{^}}v_add_nc_u64 v[4:5], v[2:3], v[4:5] quad_perm:[3,2,1,0]
56+
// GFX1251-ERR-NEXT:{{^}} ^
57+
58+
v_sub_nc_u64 v[4:5], v[2:3], v[4:5] quad_perm:[3,2,1,0]
59+
// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: DP ALU dpp only supports row_share
60+
// GFX1251-ERR-NEXT:{{^}}v_sub_nc_u64 v[4:5], v[2:3], v[4:5] quad_perm:[3,2,1,0]
61+
// GFX1251-ERR-NEXT:{{^}} ^
62+
63+
v_fmac_f64 v[4:5], v[2:3], v[4:5] quad_perm:[3,2,1,0]
64+
// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: DP ALU dpp only supports row_share
65+
// GFX1251-ERR-NEXT:{{^}}v_fmac_f64 v[4:5], v[2:3], v[4:5] quad_perm:[3,2,1,0]
66+
// GFX1251-ERR-NEXT:{{^}} ^
67+
68+
v_add_f64 v[4:5], v[2:3], v[4:5] quad_perm:[3,2,1,0]
69+
// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: DP ALU dpp only supports row_share
70+
// GFX1251-ERR-NEXT:{{^}}v_add_f64 v[4:5], v[2:3], v[4:5] quad_perm:[3,2,1,0]
71+
// GFX1251-ERR-NEXT:{{^}} ^
72+
73+
v_mul_f64 v[4:5], v[2:3], v[4:5] quad_perm:[3,2,1,0]
74+
// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: DP ALU dpp only supports row_share
75+
// GFX1251-ERR-NEXT:{{^}}v_mul_f64 v[4:5], v[2:3], v[4:5] quad_perm:[3,2,1,0]
76+
// GFX1251-ERR-NEXT:{{^}} ^
77+
78+
v_max_num_f64 v[4:5], v[2:3], v[4:5] quad_perm:[3,2,1,0]
79+
// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: DP ALU dpp only supports row_share
80+
// GFX1251-ERR-NEXT:{{^}}v_max_num_f64 v[4:5], v[2:3], v[4:5] quad_perm:[3,2,1,0]
81+
// GFX1251-ERR-NEXT:{{^}} ^
82+
83+
v_min_num_f64 v[4:5], v[2:3], v[4:5] quad_perm:[3,2,1,0]
84+
// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: DP ALU dpp only supports row_share
85+
// GFX1251-ERR-NEXT:{{^}}v_min_num_f64 v[4:5], v[2:3], v[4:5] quad_perm:[3,2,1,0]
86+
// GFX1251-ERR-NEXT:{{^}} ^
87+
88+
v_lshlrev_b64 v[4:5], v2, v[4:5] quad_perm:[3,2,1,0]
89+
// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: DP ALU dpp only supports row_share
90+
// GFX1251-ERR-NEXT:{{^}}v_lshlrev_b64 v[4:5], v2, v[4:5] quad_perm:[3,2,1,0]
91+
// GFX1251-ERR-NEXT:{{^}} ^
92+
93+
v_mul_u64 v[2:3], v[4:5], v[6:7] row_share:1
94+
// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
95+
// GFX1251-ERR-NEXT:{{^}}v_mul_u64 v[2:3], v[4:5], v[6:7] row_share:1
96+
// GFX1251-ERR-NEXT:{{^}} ^
97+
98+
v_fmamk_f64 v[4:5], v[2:3], 123.0, v[6:7] row_share:1
99+
// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
100+
// GFX1251-ERR-NEXT:{{^}}v_fmamk_f64 v[4:5], v[2:3], 123.0, v[6:7] row_share:1
101+
// GFX1251-ERR-NEXT:{{^}} ^
102+
103+
v_fmaak_f64 v[4:5], v[2:3], v[6:7], 123.0 row_share:1
104+
// GFX1251-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
105+
// GFX1251-ERR-NEXT:{{^}}v_fmaak_f64 v[4:5], v[2:3], v[6:7], 123.0 row_share:1
106+
// GFX1251-ERR-NEXT:{{^}} ^

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