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[AMDGPU] clang-tidy: use emplace_back instead of push_back. NFC.
1 parent d3dab0c commit 5e338f1

12 files changed

+34
-38
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -285,7 +285,7 @@ void AMDGPUAsmPrinter::emitFunctionEntryLabel() {
285285
// Disassemble function name label to text.
286286
DisasmLines.push_back(MF->getName().str() + ":");
287287
DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLines.back().size());
288-
HexLines.push_back("");
288+
HexLines.emplace_back("");
289289
}
290290

291291
AsmPrinter::emitFunctionEntryLabel();
@@ -298,7 +298,7 @@ void AMDGPUAsmPrinter::emitBasicBlockStart(const MachineBasicBlock &MBB) {
298298
(Twine("BB") + Twine(getFunctionNumber())
299299
+ "_" + Twine(MBB.getNumber()) + ":").str());
300300
DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLines.back().size());
301-
HexLines.push_back("");
301+
HexLines.emplace_back("");
302302
}
303303
AsmPrinter::emitBasicBlockStart(MBB);
304304
}

‎llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2466,7 +2466,7 @@ int SchedGroup::link(SUnit &SU, bool MakePred,
24662466
// the A->B edge impossible, otherwise it returns true;
24672467
bool Added = tryAddEdge(A, B);
24682468
if (Added)
2469-
AddedEdges.push_back(std::pair(A, B));
2469+
AddedEdges.emplace_back(A, B);
24702470
else
24712471
++MissedEdges;
24722472
}

‎llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -480,7 +480,7 @@ doPartitioning(SplitModuleLogger &SML, Module &M, unsigned NumParts,
480480
// partitions) so it's a cheap operation.
481481
std::vector<std::pair<PartitionID, CostType>> BalancingQueue;
482482
for (unsigned I = 0; I < NumParts; ++I)
483-
BalancingQueue.push_back(std::make_pair(I, 0));
483+
BalancingQueue.emplace_back(I, 0);
484484

485485
// Helper function to handle assigning a function to a partition. This takes
486486
// care of updating the balancing queue.

‎llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -169,7 +169,7 @@ BasicBlock *AMDGPUUnifyDivergentExitNodesImpl::unifyReturnBlockSet(
169169
// Remove and delete the return inst.
170170
BB->getTerminator()->eraseFromParent();
171171
BranchInst::Create(NewRetBlock, BB);
172-
Updates.push_back({DominatorTree::Insert, BB, NewRetBlock});
172+
Updates.emplace_back(DominatorTree::Insert, BB, NewRetBlock);
173173
}
174174

175175
if (RequireAndPreserveDomTree)
@@ -239,7 +239,7 @@ bool AMDGPUUnifyDivergentExitNodesImpl::run(Function &F, DominatorTree *DT,
239239
BI->eraseFromParent(); // Delete the unconditional branch.
240240
// Add a new conditional branch with a dummy edge to the return block.
241241
BranchInst::Create(LoopHeaderBB, DummyReturnBB, BoolTrue, BB);
242-
Updates.push_back({DominatorTree::Insert, BB, DummyReturnBB});
242+
Updates.emplace_back(DominatorTree::Insert, BB, DummyReturnBB);
243243
} else { // Conditional branch.
244244
SmallVector<BasicBlock *, 2> Successors(successors(BB));
245245

@@ -250,17 +250,17 @@ bool AMDGPUUnifyDivergentExitNodesImpl::run(Function &F, DominatorTree *DT,
250250

251251
// 'Successors' become successors of TransitionBB instead of BB,
252252
// and TransitionBB becomes a single successor of BB.
253-
Updates.push_back({DominatorTree::Insert, BB, TransitionBB});
253+
Updates.emplace_back(DominatorTree::Insert, BB, TransitionBB);
254254
for (BasicBlock *Successor : Successors) {
255-
Updates.push_back({DominatorTree::Insert, TransitionBB, Successor});
256-
Updates.push_back({DominatorTree::Delete, BB, Successor});
255+
Updates.emplace_back(DominatorTree::Insert, TransitionBB, Successor);
256+
Updates.emplace_back(DominatorTree::Delete, BB, Successor);
257257
}
258258

259259
// Create a branch that will always branch to the transition block and
260260
// references DummyReturnBB.
261261
BB->getTerminator()->eraseFromParent();
262262
BranchInst::Create(TransitionBB, DummyReturnBB, BoolTrue, BB);
263-
Updates.push_back({DominatorTree::Insert, BB, DummyReturnBB});
263+
Updates.emplace_back(DominatorTree::Insert, BB, DummyReturnBB);
264264
}
265265
Changed = true;
266266
}
@@ -281,7 +281,7 @@ bool AMDGPUUnifyDivergentExitNodesImpl::run(Function &F, DominatorTree *DT,
281281
// Remove and delete the unreachable inst.
282282
BB->getTerminator()->eraseFromParent();
283283
BranchInst::Create(UnreachableBlock, BB);
284-
Updates.push_back({DominatorTree::Insert, BB, UnreachableBlock});
284+
Updates.emplace_back(DominatorTree::Insert, BB, UnreachableBlock);
285285
}
286286
Changed = true;
287287
}

‎llvm/lib/Target/AMDGPU/R600EmitClauseMarkers.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -133,20 +133,20 @@ class R600EmitClauseMarkers : public MachineFunctionPass {
133133
const std::pair<unsigned, unsigned> &BankLine = getAccessedBankLine(Sel);
134134
if (CachedConsts.empty()) {
135135
CachedConsts.push_back(BankLine);
136-
UsedKCache.push_back(std::pair<unsigned, unsigned>(0, KCacheIndex));
136+
UsedKCache.emplace_back(0, KCacheIndex);
137137
continue;
138138
}
139139
if (CachedConsts[0] == BankLine) {
140-
UsedKCache.push_back(std::pair<unsigned, unsigned>(0, KCacheIndex));
140+
UsedKCache.emplace_back(0, KCacheIndex);
141141
continue;
142142
}
143143
if (CachedConsts.size() == 1) {
144144
CachedConsts.push_back(BankLine);
145-
UsedKCache.push_back(std::pair<unsigned, unsigned>(1, KCacheIndex));
145+
UsedKCache.emplace_back(1, KCacheIndex);
146146
continue;
147147
}
148148
if (CachedConsts[1] == BankLine) {
149-
UsedKCache.push_back(std::pair<unsigned, unsigned>(1, KCacheIndex));
149+
UsedKCache.emplace_back(1, KCacheIndex);
150150
continue;
151151
}
152152
return false;

‎llvm/lib/Target/AMDGPU/R600InstrInfo.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -326,11 +326,11 @@ R600InstrInfo::ExtractSrcs(MachineInstr &MI,
326326
Register Reg = Src.first->getReg();
327327
int Index = RI.getEncodingValue(Reg) & 0xff;
328328
if (Reg == R600::OQAP) {
329-
Result.push_back(std::pair(Index, 0U));
329+
Result.emplace_back(Index, 0U);
330330
}
331331
if (PV.contains(Reg)) {
332332
// 255 is used to tells its a PS/PV reg
333-
Result.push_back(std::pair(255, 0U));
333+
Result.emplace_back(255, 0U);
334334
continue;
335335
}
336336
if (Index > 127) {
@@ -339,7 +339,7 @@ R600InstrInfo::ExtractSrcs(MachineInstr &MI,
339339
continue;
340340
}
341341
unsigned Chan = RI.getHWRegChan(Reg);
342-
Result.push_back(std::pair(Index, Chan));
342+
Result.emplace_back(Index, Chan);
343343
}
344344
for (; i < 3; ++i)
345345
Result.push_back(DummyPair);

‎llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -58,7 +58,7 @@ class RegSeqInfo {
5858
MachineOperand &MO = Instr->getOperand(i);
5959
unsigned Chan = Instr->getOperand(i + 1).getImm();
6060
if (isImplicitlyDef(MRI, MO.getReg()))
61-
UndefReg.push_back(Chan);
61+
UndefReg.emplace_back(Chan);
6262
else
6363
RegToChan[MO.getReg()] = Chan;
6464
}
@@ -154,14 +154,12 @@ bool R600VectorRegMerger::tryMergeVector(const RegSeqInfo *Untouched,
154154
DenseMap<Register, unsigned>::const_iterator PosInUntouched =
155155
Untouched->RegToChan.find(It.first);
156156
if (PosInUntouched != Untouched->RegToChan.end()) {
157-
Remap.push_back(
158-
std::pair<unsigned, unsigned>(It.second, (*PosInUntouched).second));
157+
Remap.emplace_back(It.second, (*PosInUntouched).second);
159158
continue;
160159
}
161160
if (CurrentUndexIdx >= Untouched->UndefReg.size())
162161
return false;
163-
Remap.push_back(std::pair<unsigned, unsigned>(
164-
It.second, Untouched->UndefReg[CurrentUndexIdx++]));
162+
Remap.emplace_back(It.second, Untouched->UndefReg[CurrentUndexIdx++]);
165163
}
166164

167165
return true;

‎llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -237,7 +237,7 @@ bool SILowerSGPRSpills::spillCalleeSavedRegs(
237237
int JunkFI = MFI.CreateStackObject(TRI->getSpillSize(*RC),
238238
TRI->getSpillAlign(*RC), true);
239239

240-
CSI.push_back(CalleeSavedInfo(Reg, JunkFI));
240+
CSI.emplace_back(Reg, JunkFI);
241241
CalleeSavedFIs.push_back(JunkFI);
242242
}
243243
}

‎llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -358,8 +358,7 @@ bool SIMachineFunctionInfo::allocateVirtualVGPRForSGPRSpills(
358358
LaneVGPR = SpillVGPRs.back();
359359
}
360360

361-
SGPRSpillsToVirtualVGPRLanes[FI].push_back(
362-
SIRegisterInfo::SpilledReg(LaneVGPR, LaneIndex));
361+
SGPRSpillsToVirtualVGPRLanes[FI].emplace_back(LaneVGPR, LaneIndex);
363362
return true;
364363
}
365364

@@ -393,8 +392,7 @@ bool SIMachineFunctionInfo::allocatePhysicalVGPRForSGPRSpills(
393392
LaneVGPR = SpillPhysVGPRs.back();
394393
}
395394

396-
SGPRSpillsToPhysicalVGPRLanes[FI].push_back(
397-
SIRegisterInfo::SpilledReg(LaneVGPR, LaneIndex));
395+
SGPRSpillsToPhysicalVGPRLanes[FI].emplace_back(LaneVGPR, LaneIndex);
398396
return true;
399397
}
400398

‎llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -546,7 +546,7 @@ void SIScheduleBlock::addSucc(SIScheduleBlock *Succ,
546546
}
547547
if (Succ->isHighLatencyBlock())
548548
++NumHighLatencySuccessors;
549-
Succs.push_back(std::pair(Succ, Kind));
549+
Succs.emplace_back(Succ, Kind);
550550

551551
assert(none_of(Preds,
552552
[=](SIScheduleBlock *P) { return SuccID == P->getID(); }) &&

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