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Merge pull request #5 from demik/main
PCB panels + TashTwenty Tiny v1.1
2 parents 5749d25 + 73b13ec commit 86f1e76

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‎pcb/TashTwenty Tiny/.gitignore‎

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# OS X
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.DS_Store
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.AppleDouble
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.LSOverride
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Icon
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17
# tmp zip files
28
*.zip
39

‎pcb/TashTwenty Tiny/Panels/Back/TTT_BP.kicad_pcb‎

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‎pcb/TashTwenty Tiny/Panels/Back/TTT_BP.pro‎

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update=2022 March 31, Thursday 19:42:15
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version=1
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last_client=kicad
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[general]
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version=1
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RootSch=
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BoardNm=
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[cvpcb]
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version=1
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NetIExt=net
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[eeschema]
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version=1
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LibDir=
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[eeschema/libraries]
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[pcbnew]
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version=1
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PageLayoutDescrFile=
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LastNetListRead=
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CopperLayerCount=2
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BoardThickness=1.6
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AllowMicroVias=0
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AllowBlindVias=0
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RequireCourtyardDefinitions=0
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ProhibitOverlappingCourtyards=1
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MinTrackWidth=0.2
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MinViaDiameter=0.4
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MinViaDrill=0.3
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MinMicroViaDiameter=0.2
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MinMicroViaDrill=0.09999999999999999
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MinHoleToHole=0.25
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TrackWidth1=0.25
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ViaDiameter1=0.8
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ViaDrill1=0.4
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dPairWidth1=0.2
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dPairGap1=0.25
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dPairViaGap1=0.25
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SilkLineWidth=0.12
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SilkTextSizeV=1
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SilkTextSizeH=1
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SilkTextSizeThickness=0.15
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SilkTextItalic=0
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SilkTextUpright=1
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CopperLineWidth=0.2
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CopperTextSizeV=1.5
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CopperTextSizeH=1.5
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CopperTextThickness=0.3
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CopperTextItalic=0
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CopperTextUpright=1
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EdgeCutLineWidth=0.05
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CourtyardLineWidth=0.05
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OthersLineWidth=0.15
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OthersTextSizeV=1
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OthersTextSizeH=1
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OthersTextSizeThickness=0.15
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OthersTextItalic=0
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OthersTextUpright=1
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SolderMaskClearance=0
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SolderMaskMinWidth=0
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SolderPasteClearance=0
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SolderPasteRatio=-0
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[pcbnew/Layer.F.Cu]
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Name=F.Cu
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Type=0
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Enabled=1
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[pcbnew/Layer.In1.Cu]
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Name=In1.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In2.Cu]
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Name=In2.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In3.Cu]
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Name=In3.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In4.Cu]
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Name=In4.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In5.Cu]
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Name=In5.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In6.Cu]
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Name=In6.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In7.Cu]
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Name=In7.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In8.Cu]
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Name=In8.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In9.Cu]
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Name=In9.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In10.Cu]
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Name=In10.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In11.Cu]
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Name=In11.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In12.Cu]
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Name=In12.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In13.Cu]
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Name=In13.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In14.Cu]
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Name=In14.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In15.Cu]
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Name=In15.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In16.Cu]
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Name=In16.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In17.Cu]
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Name=In17.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In18.Cu]
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Name=In18.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In19.Cu]
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Name=In19.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In20.Cu]
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Name=In20.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In21.Cu]
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Name=In21.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In22.Cu]
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Name=In22.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In23.Cu]
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Name=In23.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In24.Cu]
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Name=In24.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In25.Cu]
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Name=In25.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In26.Cu]
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Name=In26.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In27.Cu]
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Name=In27.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In28.Cu]
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Name=In28.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In29.Cu]
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Name=In29.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In30.Cu]
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Name=In30.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.B.Cu]
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Name=B.Cu
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Type=0
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Enabled=1
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[pcbnew/Layer.B.Adhes]
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Enabled=0
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[pcbnew/Layer.F.Adhes]
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Enabled=0
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[pcbnew/Layer.B.Paste]
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Enabled=0
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[pcbnew/Layer.F.Paste]
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Enabled=0
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[pcbnew/Layer.B.SilkS]
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Enabled=1
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[pcbnew/Layer.F.SilkS]
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Enabled=1
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[pcbnew/Layer.B.Mask]
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Enabled=1
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[pcbnew/Layer.F.Mask]
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Enabled=1
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[pcbnew/Layer.Dwgs.User]
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Enabled=1
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[pcbnew/Layer.Cmts.User]
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Enabled=1
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[pcbnew/Layer.Eco1.User]
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Enabled=0
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[pcbnew/Layer.Eco2.User]
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Enabled=0
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[pcbnew/Layer.Edge.Cuts]
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Enabled=1
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[pcbnew/Layer.Margin]
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Enabled=1
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[pcbnew/Layer.B.CrtYd]
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Enabled=1
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[pcbnew/Layer.F.CrtYd]
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Enabled=1
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[pcbnew/Layer.B.Fab]
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Enabled=1
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[pcbnew/Layer.F.Fab]
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Enabled=1
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[pcbnew/Layer.Rescue]
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Enabled=0
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[pcbnew/Netclasses]
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[pcbnew/Netclasses/Default]
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Name=Default
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Clearance=0.2
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TrackWidth=0.25
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ViaDiameter=0.8
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ViaDrill=0.4
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uViaDiameter=0.3
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uViaDrill=0.1
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dPairWidth=0.2
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dPairGap=0.25
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dPairViaGap=0.25

‎pcb/TashTwenty Tiny/Panels/Back/TTT_BP.sch‎

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EESchema Schematic File Version 4
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EELAYER 30 0
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EELAYER END
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$Descr A4 11693 8268
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encoding utf-8
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Sheet 1 1
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Title ""
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Date "2022-05-17"
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Rev "1.0"
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Comp ""
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Comment1 ""
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Comment2 ""
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Comment3 ""
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Comment4 ""
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$EndDescr
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$Comp
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L Connector:TestPoint TP1
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U 1 1 6246096F
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P 6000 5000
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F 0 "TP1" H 6058 5118 50 0000 L CNN
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F 1 "TestPoint" H 6058 5027 50 0000 L CNN
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F 2 "TestPoint:TestPoint_Pad_1.5x1.5mm" H 6200 5000 50 0001 C CNN
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F 3 "~" H 6200 5000 50 0001 C CNN
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1 6000 5000
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1 0 0 -1
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$EndComp
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Wire Wire Line
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6000 5000 6000 5250
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$Comp
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L power:PWR_FLAG #FLG0101
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U 1 1 6245F89A
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P 5500 5000
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F 0 "#FLG0101" H 5500 5075 50 0001 C CNN
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F 1 "PWR_FLAG" H 5500 5173 50 0000 C CNN
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F 2 "" H 5500 5000 50 0001 C CNN
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F 3 "~" H 5500 5000 50 0001 C CNN
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1 5500 5000
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1 0 0 -1
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$EndComp
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Wire Wire Line
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5500 5000 5500 5250
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Wire Wire Line
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5500 5250 6000 5250
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Connection ~ 6000 5250
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Wire Wire Line
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6000 5250 6000 5500
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$Comp
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L Connector:TestPoint TP2
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U 1 1 6245FB73
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P 6000 4500
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F 0 "TP2" H 6058 4618 50 0000 L CNN
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F 1 "TestPoint" H 6058 4527 50 0000 L CNN
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F 2 "TestPoint:TestPoint_Pad_1.5x1.5mm" H 6200 4500 50 0001 C CNN
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F 3 "~" H 6200 4500 50 0001 C CNN
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1 6000 4500
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1 0 0 -1
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$EndComp
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Wire Wire Line
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6000 4500 6000 5000
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Connection ~ 6000 5000
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$Comp
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L power:Earth #PWR0101
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U 1 1 62460A5C
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P 6000 5500
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F 0 "#PWR0101" H 6000 5250 50 0001 C CNN
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F 1 "Earth" H 6000 5350 50 0001 C CNN
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F 2 "" H 6000 5500 50 0001 C CNN
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F 3 "~" H 6000 5500 50 0001 C CNN
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1 6000 5500
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1 0 0 -1
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$EndComp
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$EndSCHEMATC

‎pcb/TashTwenty Tiny/Panels/Back/logo.kicad_mod‎

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(module LOGO (layer F.Cu)
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(at 0 0)
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(fp_text reference "G***" (at 0 0) (layer F.SilkS) hide
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(effects (font (thickness 0.3)))
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)
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(fp_text value "LOGO" (at 0.75 0) (layer F.SilkS) hide
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(effects (font (thickness 0.3)))
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)
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(fp_poly (pts (xy 5.270500 1.079500) (xy 5.270500 3.619500) (xy 4.953000 3.619500) (xy 4.953000 3.937000) (xy -4.572000 3.937000) (xy -4.572000 3.619500) (xy -4.889500 3.619500) (xy -4.889500 1.079500)
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(xy 5.270500 1.079500) )(layer F.SilkS) (width 0.010000)
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)
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)

‎pcb/TashTwenty Tiny/Panels/Back/logo.png‎

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