[CIR][Lowering] Lower CIR ptrmask to LLVM ptrmask (llvm#1663)

LLVM dialect now has ptrmask intrinsic, use it instead of the manual
computation

Fix bitwidth of the generated mask in ABIInfoImpl

Author: Jezurko

clang/include/clang/CIR/Dialect/IR/CIROps.td

@@ -4933,6 +4933,8 @@ def PtrMaskOp : CIR_Op<"ptr_mask", [AllTypesMatch<["ptr", "result"]>]> {
   let assemblyFormat = [{
     `(` $ptr `,` $mask `:` type($mask) `)` `:` qualified(type($result)) attr-dict
   }];
+
+  let llvmOp = "PtrMaskOp";
 }
 
 //===----------------------------------------------------------------------===//

clang/lib/CIR/Dialect/Transforms/TargetLowering/ABIInfoImpl.cpp

@@ -43,9 +43,11 @@ mlir::Value emitRoundPointerUpToAlignment(cir::CIRBaseBuilderTy &builder,
   mlir::Value roundUp = builder.createPtrStride(
       loc, builder.createPtrBitcast(ptr, builder.getUIntNTy(8)),
       builder.getUnsignedInt(loc, alignment - 1, /*width=*/32));
+  auto dataLayout = mlir::DataLayout::closest(roundUp.getDefiningOp());
   return builder.create<cir::PtrMaskOp>(
       loc, roundUp.getType(), roundUp,
-      builder.getSignedInt(loc, -(signed)alignment, /*width=*/32));
+      builder.getSignedInt(loc, -(signed)alignment,
+                           dataLayout.getTypeSizeInBits(roundUp.getType())));
 }
 
 mlir::Type useFirstFieldIfTransparentUnion(mlir::Type Ty) {

clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp

@@ -4206,32 +4206,6 @@ mlir::LogicalResult CIRToLLVMAbsOpLowering::matchAndRewrite(
   return mlir::success();
 }
 
-mlir::LogicalResult CIRToLLVMPtrMaskOpLowering::matchAndRewrite(
-    cir::PtrMaskOp op, OpAdaptor adaptor,
-    mlir::ConversionPatternRewriter &rewriter) const {
-  // FIXME: We'd better to lower to mlir::LLVM::PtrMaskOp if it exists.
-  // So we have to make it manually here by following:
-  // https://llvm.org/docs/LangRef.html#llvm-ptrmask-intrinsic
-  auto loc = op.getLoc();
-  auto mask = op.getMask();
-
-  auto moduleOp = op->getParentOfType<mlir::ModuleOp>();
-  mlir::DataLayout layout(moduleOp);
-  auto iPtrIdxValue = layout.getTypeSizeInBits(mask.getType());
-  auto iPtrIdx = mlir::IntegerType::get(moduleOp->getContext(), iPtrIdxValue);
-
-  auto intPtr = rewriter.create<mlir::LLVM::PtrToIntOp>(
-      loc, iPtrIdx, adaptor.getPtr()); // this may truncate
-  mlir::Value masked =
-      rewriter.create<mlir::LLVM::AndOp>(loc, intPtr, adaptor.getMask());
-  mlir::Value diff = rewriter.create<mlir::LLVM::SubOp>(loc, intPtr, masked);
-  rewriter.replaceOpWithNewOp<mlir::LLVM::GEPOp>(
-      op, getTypeConverter()->convertType(op.getType()),
-      mlir::IntegerType::get(moduleOp->getContext(), 8), adaptor.getPtr(),
-      diff);
-  return mlir::success();
-}
-
 mlir::LogicalResult CIRToLLVMSignBitOpLowering::matchAndRewrite(
     cir::SignBitOp op, OpAdaptor adaptor,
     mlir::ConversionPatternRewriter &rewriter) const {
@@ -4364,7 +4338,6 @@ void populateCIRToLLVMConversionPatterns(
       CIRToLLVMObjSizeOpLowering,
       CIRToLLVMPrefetchOpLowering,
       CIRToLLVMPtrDiffOpLowering,
-      CIRToLLVMPtrMaskOpLowering,
       CIRToLLVMResumeOpLowering,
       CIRToLLVMReturnAddrOpLowering,
       CIRToLLVMRotateOpLowering,

clang/test/CIR/Lowering/var-arg-x86_64.c

@@ -95,10 +95,7 @@ long double f2(int n, ...) {
 // CHECK: [[OVERFLOW_AREA:%.+]] = load ptr, ptr [[OVERFLOW_AREA_P]]
 // Ptr Mask Operations
 // CHECK: [[OVERFLOW_AREA_OFFSET_ALIGNED:%.+]] = getelementptr i8, ptr [[OVERFLOW_AREA]], i64 15
-// CHECK: [[OVERFLOW_AREA_OFFSET_ALIGNED_P:%.+]] = ptrtoint ptr [[OVERFLOW_AREA_OFFSET_ALIGNED]] to i32
-// CHECK: [[MASKED:%.+]] = and i32 [[OVERFLOW_AREA_OFFSET_ALIGNED_P]], -16
-// CHECK: [[DIFF:%.+]] = sub i32 [[OVERFLOW_AREA_OFFSET_ALIGNED_P]], [[MASKED]]
-// CHECK: [[PTR_MASKED:%.+]] = getelementptr i8, ptr [[OVERFLOW_AREA_OFFSET_ALIGNED]], i32 [[DIFF]]
+// CHECK: [[PTR_MASKED:%.+]] = call ptr @llvm.ptrmask.{{.*}}.[[PTR_SIZE_INT:.*]](ptr [[OVERFLOW_AREA_OFFSET_ALIGNED]], [[PTR_SIZE_INT]] -16)
 // CHECK: [[OVERFLOW_AREA_NEXT:%.+]] = getelementptr i8, ptr [[PTR_MASKED]], i64 16
 // CHECK: store ptr [[OVERFLOW_AREA_NEXT]], ptr [[OVERFLOW_AREA_P]]
 // CHECK: [[VALUE:%.+]] = load x86_fp80, ptr [[PTR_MASKED]]