Not able to run the examples with spike to probe the csr

[sambhavjain12]

I am trying to use the riscv-probe with spike simulator. I cloned riscv-probe and then ran the make command, to generate object files.
Then I ran the command

$ spike --isa=RV64IMAFDC build/bin/rv64imac/spike/probe
isa: rv64imafdcsu
csr: fflags          illegal_instruction cause=2 mtval=0x0000000000000000
csr: frm             illegal_instruction cause=2 mtval=0x0000000000000000
csr: fcsr            illegal_instruction cause=2 mtval=0x0000000000000000
csr: mcycle          0x0000000000123d27
csr: minstret        0x0000000000154a64
csr: mcycleh         illegal_instruction cause=2 mtval=0x0000000000000000
csr: minstreth       illegal_instruction cause=2 mtval=0x0000000000000000
csr: cycle           0x0000000000237bbf
csr: time            illegal_instruction cause=2 mtval=0x0000000000000000
csr: instret         0x00000000002c1b12
csr: cycleh          illegal_instruction cause=2 mtval=0x0000000000000000
csr: timeh           illegal_instruction cause=2 mtval=0x0000000000000000
csr: instreth        illegal_instruction cause=2 mtval=0x0000000000000000
csr: mvendorid       0x0000000000000000
csr: marchid         0x0000000000000005
csr: mimpid          0x0000000000000000
csr: mhartid         0x0000000000000000
csr: mstatus         0x0000000a00000080
csr: misa            0x800000000014112d
csr: medeleg         0x0000000000000000
csr: mideleg         0x0000000000000000
csr: mie             0x0000000000000000
csr: mtvec           0x000000008000002c
csr: mcounteren      0x0000000000000000
csr: mscratch        0x0000000000000000
csr: mepc            0x00000000800002c4
csr: mcause          0x0000000000000002
csr: mtval           0x0000000000000000
csr: mip             0x0000000000000080
csr: sstatus         0x0000000200000000
csr: sedeleg         illegal_instruction cause=2 mtval=0x0000000000000000
csr: sideleg         illegal_instruction cause=2 mtval=0x0000000000000000
csr: sie             0x0000000000000000
csr: stvec           0x0000000000000000
csr: scounteren      0x0000000000000000
csr: sscratch        0x0000000000000000
csr: sepc            0x0000000000000000
csr: scause          0x0000000000000000
csr: stval           0x0000000000000000
csr: sip             0x0000000000000000
csr: satp            0x0000000000000000
csr: pmpcfg0         0x000000000000001f
csr: pmpcfg1         illegal_instruction cause=2 mtval=0x0000000000000000
csr: pmpcfg2         0x0000000000000000
csr: pmpcfg3         illegal_instruction cause=2 mtval=0x0000000000000000
csr: pmpaddr0        0xffffffffffffffff
csr: pmpaddr1        0x0000000000000000
csr: pmpaddr2        0x0000000000000000
csr: pmpaddr3        0x0000000000000000
csr: pmpaddr4        0x0000000000000000
csr: pmpaddr5        0x0000000000000000
csr: pmpaddr6        0x0000000000000000
csr: pmpaddr7        0x0000000000000000
csr: pmpaddr8        0x0000000000000000
csr: pmpaddr9        0x0000000000000000
csr: pmpaddr10       0x0000000000000000
csr: pmpaddr11       0x0000000000000000
csr: pmpaddr12       0x0000000000000000
csr: pmpaddr13       0x0000000000000000
csr: pmpaddr14       0x0000000000000000
csr: pmpaddr15       0x0000000000000000

Succesfully getting all the CSR, but I wasn't able to run any of the examples, since I am new to spike simulator I couldn't find steps or commands in your documentation to run any of your examples.

Still I tried running the examples as,
1)

 $ spike build/obj/rv64imac/examples/hello/hello.o 
warning: tohost and fromhost symbols not in ELF; can't communicate with target

$ spike  build/obj/rv64imac/examples/hello/hello.o 
warning: tohost and fromhost symbols not in ELF; can't communicate with target

$ spike $(which pk)  build/obj/rv64imac/examples/hello/hello.o --isa=RV64IMAFDC build/bin/rv64imac/spike/probe 
z  0000000000000000 ra 0000000000000000 sp 000000007f7e9af0 gp 0000000000000000
tp 0000000000000000 t0 0000000000000000 t1 0000000000000000 t2 0000000000000000
s0 0000000000000000 s1 0000000000000000 a0 0000000000000000 a1 0000000000000000
a2 0000000000000000 a3 0000000000000000 a4 0000000000000000 a5 0000000000000000
a6 0000000000000000 a7 0000000000000000 s2 0000000000000000 s3 0000000000000000
s4 0000000000000000 s5 0000000000000000 s6 0000000000000000 s7 0000000000000000
s8 0000000000000000 s9 0000000000000000 sA 0000000000000000 sB 0000000000000000
t3 0000000000000000 t4 0000000000000000 t5 0000000000000000 t6 0000000000000000
pc 0000000000000000 va 0000000000000000 insn       ffffffff sr 8000000200046020
User fetch segfault @ 0x0000000000000000

Unfortunately I am not able to run any of your example code's object file using spike or even with spike-pk It would be great if you could help me out, in running the riscv-probe properly, since my application requires to run and probe the CSR registers.
It would be also great if you could include it in README file, for everyone to use.