about the full and empty signals

[jyx-whu]

Are the full and empty signals here actually almost full/empty?

[lauchinyuan]

The full and empty signals in this design do not reflect the 'almost full' and 'almost empty'. I suspect they may not be accurately indicating the current FIFO status. Have you considered the cycle latencies introduced by the clock domain crossing when processing the read/write pointers? Let me know if you need further help.

[ZZQ30]

您好：
async_fifo
#(.RAM_DEPTH ( 'd1024 ) ,
.RAM_ADDR_WIDTH ( 'd10 ) ,
.WR_WIDTH ( 'd32 ) ,
.RD_WIDTH ( 'd16 ) ,
.WR_IND ( 'd2 ) ,
.RD_IND ( 'd1 ) ,
.RAM_WIDTH ( 'd16 ) ,
.WR_L2 ( 'd1 ) ,
.RD_L2 ( 'd0 ) ,
.WR_CNT_WIDTH ( 'd10 + 'd1 - 'd1 ) ,
.RD_CNT_WIDTH ( 'd10 + 'd1 - 0 ) ,
.RAM_RD2WR ( 'd1 )
）
inst_rd_async_fifo
(

   .  wr_clk         (clk) ,
   .  wr_rst_n       (~rdfifo_clr) ,
   .  wr_en          (rdfifo_wren) ,
   .  wr_data        (rdfifo_din) , 
   .  fifo_full      (rdfifo_full) ,
   .  wr_data_count  (rdfifo_wr_cnt)
                                     
   .  rd_clk         (rdfifo_clk) , 
   .  rd_rst_n       (~rdfifo_clr) ,
   .  rd_en          (rdfifo_rden) ,
   .  rd_data        (rdfifo_dout) ,
   .  fifo_empty     (rdfifo_empty) ,
   .  rd_data_count  (rdfifo_rd_cnt)
);          

以上是 我在 例化中设置的参数，写时钟为200M，读时钟为50M，写位宽为32，读位宽16
我使用这个模块我的lcd屏上是显示黑屏，而我将这个模块替换为vivado自带的ip核就能正常显示

我的工程是与ddr读写方面的，用到了两个FIFO，一个FIFO（记为写FIFO）用于外部摄像头写入ddr, 另一个FIFO（记为读FIFO）用于ddr读出，显示到lcd屏。
我将写fifo ip核替换为您的代码，是可以正常使用的，但是我将读fifo ip核替换为您的代码，却出现了问题，上述代码是读FIFO IP的例化参数。

我看您在ddr_ctrl工程中，例化的FIFO的写位宽和读位宽是相等的，如果他们不相等，会不会和我一样出现问题呢

[lauchinyuan]

@ZZQ30
Actually, I have conducted some experiments where WR_WIDTH ≠ RD_WIDTH, and it worked fine. Therefore, I suspect there might be some issues with your project.
I suggest following these steps to help identify the bug:

1. Run a simulation of the Asymmetric-Async FIFO project with WR_WIDTH ≠ RD_WIDTH to check whether the error originates from my project.
2. Use the ILA IP to capture runtime waveforms and verify the FIFO's functionality.
3. Ensure that there are no other issues in your project that might be causing the problem.