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[Clang][LLVM][AArch64] Add intrinsic for LUTI4 SME2 instruction (llvm#97755) (llvm#109953)
This patch was reverted because of a failing C test. It now has being solved and can be merged into main again This patch adds these intrinsics: // Variants are also available for: _s8 svuint8x4_t svluti4_zt_u8_x4(uint64_t zt0, svuint8x2_t zn) __arm_streaming __arm_in("zt0"); according to PR#324[1] [1]ARM-software/acle#324
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‎clang/include/clang/Basic/arm_sme.td‎

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@@ -817,4 +817,9 @@ multiclass ZAReadzArray<string vg_num>{
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defm SVREADZ_VG2 : ZAReadzArray<"2">;
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defm SVREADZ_VG4 : ZAReadzArray<"4">;
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let SMETargetGuard = "sme2,sme-lutv2" in {
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def SVLUTI4_ZT_X4 : SInst<"svluti4_zt_{d}_x4", "4i2.u", "cUc", MergeNone, "aarch64_sme_luti4_zt_x4", [IsStreaming, IsInZT0], [ImmCheck<0, ImmCheck0_0>]>;
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}
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} // let SVETargetGuard = InvalidMode

‎clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_zt.c‎

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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
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// REQUIRES: aarch64-registered-target
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -o /dev/null %s
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#include <arm_sme.h>
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// CHECK-LABEL: define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_luti4_zt_u8_x4(
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// CHECK-SAME: <vscale x 16 x i8> [[OP_COERCE0:%.*]], <vscale x 16 x i8> [[OP_COERCE1:%.*]]) #[[ATTR0:[0-9]+]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 0, <vscale x 16 x i8> [[OP_COERCE0]], <vscale x 16 x i8> [[OP_COERCE1]])
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// CHECK-NEXT: ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]]
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//
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// CPP-CHECK-LABEL: define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @_Z19test_luti4_zt_u8_x411svuint8x2_t(
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// CPP-CHECK-SAME: <vscale x 16 x i8> [[OP_COERCE0:%.*]], <vscale x 16 x i8> [[OP_COERCE1:%.*]]) #[[ATTR0:[0-9]+]] {
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// CPP-CHECK-NEXT: [[ENTRY:.*:]]
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// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 0, <vscale x 16 x i8> [[OP_COERCE0]], <vscale x 16 x i8> [[OP_COERCE1]])
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// CPP-CHECK-NEXT: ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]]
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//
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svuint8x4_t test_luti4_zt_u8_x4(svuint8x2_t op) __arm_streaming __arm_in("zt0") {
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return svluti4_zt_u8_x4(0, op);
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}
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// CHECK-LABEL: define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_luti4_zt_s8_x4(
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// CHECK-SAME: <vscale x 16 x i8> [[OP_COERCE0:%.*]], <vscale x 16 x i8> [[OP_COERCE1:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 0, <vscale x 16 x i8> [[OP_COERCE0]], <vscale x 16 x i8> [[OP_COERCE1]])
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// CHECK-NEXT: ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]]
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//
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// CPP-CHECK-LABEL: define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @_Z19test_luti4_zt_s8_x411svuint8x2_t(
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// CPP-CHECK-SAME: <vscale x 16 x i8> [[OP_COERCE0:%.*]], <vscale x 16 x i8> [[OP_COERCE1:%.*]]) #[[ATTR0]] {
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// CPP-CHECK-NEXT: [[ENTRY:.*:]]
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// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 0, <vscale x 16 x i8> [[OP_COERCE0]], <vscale x 16 x i8> [[OP_COERCE1]])
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// CPP-CHECK-NEXT: ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]]
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//
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svint8x4_t test_luti4_zt_s8_x4(svuint8x2_t op) __arm_streaming __arm_in("zt0") {
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return svluti4_zt_s8_x4(0, op);
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}

‎clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_imm.cpp‎

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Original file line numberDiff line numberDiff line change
@@ -350,3 +350,8 @@ void test_svdot_multi_za32_bad_lane(uint32_t slice_base, svuint16_t z_u16,
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svsudot_lane_za32_s8_vg1x2(slice_base, z_s8x2, z_u8, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
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svsudot_lane_za32_s8_vg1x4(slice_base, z_s8x4, z_u8, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
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}
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void test_luti4_zt_x4(svuint8x2_t op) __arm_streaming __arm_in("zt0") {
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// Check Zt tile 0
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svluti4_zt_u8_x4(1, op); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
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}

‎llvm/include/llvm/IR/IntrinsicsAArch64.td‎

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Original file line numberDiff line numberDiff line change
@@ -3769,6 +3769,12 @@ let TargetPrefix = "aarch64" in {
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: DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
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[llvm_i32_ty, llvm_nxv16i8_ty, llvm_i32_ty],
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[ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>, IntrReadMem]>;
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def int_aarch64_sme_luti4_zt_x4
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: DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
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[llvm_i32_ty, llvm_nxv16i8_ty, llvm_nxv16i8_ty],
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[ImmArg<ArgIndex<0>>, IntrNoMem, IntrHasSideEffects]>;
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//
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// Register scaling
@@ -3794,6 +3800,7 @@ let TargetPrefix = "aarch64" in {
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[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>,
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LLVMVectorOfBitcastsToInt<0>, LLVMVectorOfBitcastsToInt<0>, LLVMVectorOfBitcastsToInt<0>, LLVMVectorOfBitcastsToInt<0>],
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[IntrNoMem]>;
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}
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// SVE2.1 - ZIPQ1, ZIPQ2, UZPQ1, UZPQ2

‎llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp‎

Lines changed: 45 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -400,8 +400,10 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
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return SelectSVERegRegAddrMode(N, Scale, Base, Offset);
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}
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void SelectMultiVectorLuti(SDNode *Node, unsigned NumOutVecs, unsigned Opc,
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uint32_t MaxImm);
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void SelectMultiVectorLutiLane(SDNode *Node, unsigned NumOutVecs,
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unsigned Opc, uint32_t MaxImm);
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void SelectMultiVectorLuti(SDNode *Node, unsigned NumOutVecs, unsigned Opc);
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template <unsigned MaxIdx, unsigned Scale>
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bool SelectSMETileSlice(SDValue N, SDValue &Vector, SDValue &Offset) {
@@ -1975,16 +1977,18 @@ void AArch64DAGToDAGISel::SelectFrintFromVT(SDNode *N, unsigned NumVecs,
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SelectUnaryMultiIntrinsic(N, NumVecs, true, Opcode);
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}
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void AArch64DAGToDAGISel::SelectMultiVectorLuti(SDNode *Node,
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unsigned NumOutVecs,
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unsigned Opc, uint32_t MaxImm) {
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void AArch64DAGToDAGISel::SelectMultiVectorLutiLane(SDNode *Node,
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unsigned NumOutVecs,
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unsigned Opc,
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uint32_t MaxImm) {
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if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Node->getOperand(4)))
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if (Imm->getZExtValue() > MaxImm)
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return;
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SDValue ZtValue;
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if (!ImmToReg<AArch64::ZT0, 0>(Node->getOperand(2), ZtValue))
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return;
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SDValue Ops[] = {ZtValue, Node->getOperand(3), Node->getOperand(4)};
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SDLoc DL(Node);
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EVT VT = Node->getValueType(0);
@@ -2003,6 +2007,34 @@ void AArch64DAGToDAGISel::SelectMultiVectorLuti(SDNode *Node,
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CurDAG->RemoveDeadNode(Node);
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}
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void AArch64DAGToDAGISel::SelectMultiVectorLuti(SDNode *Node,
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unsigned NumOutVecs,
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unsigned Opc) {
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SDValue ZtValue;
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SmallVector<SDValue, 4> Ops;
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if (!ImmToReg<AArch64::ZT0, 0>(Node->getOperand(2), ZtValue))
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return;
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Ops.push_back(ZtValue);
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Ops.push_back(createZMulTuple({Node->getOperand(3), Node->getOperand(4)}));
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SDLoc DL(Node);
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EVT VT = Node->getValueType(0);
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SDNode *Instruction =
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CurDAG->getMachineNode(Opc, DL, {MVT::Untyped, MVT::Other}, Ops);
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SDValue SuperReg = SDValue(Instruction, 0);
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for (unsigned I = 0; I < NumOutVecs; ++I)
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ReplaceUses(SDValue(Node, I), CurDAG->getTargetExtractSubreg(
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AArch64::zsub0 + I, DL, VT, SuperReg));
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// Copy chain
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unsigned ChainIdx = NumOutVecs;
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ReplaceUses(SDValue(Node, ChainIdx), SDValue(Instruction, 1));
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CurDAG->RemoveDeadNode(Node);
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}
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void AArch64DAGToDAGISel::SelectClamp(SDNode *N, unsigned NumVecs,
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unsigned Op) {
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SDLoc DL(N);
@@ -5478,15 +5510,15 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) {
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{AArch64::LUTI2_4ZTZI_B, AArch64::LUTI2_4ZTZI_H,
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AArch64::LUTI2_4ZTZI_S}))
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// Second Immediate must be <= 3:
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SelectMultiVectorLuti(Node, 4, Opc, 3);
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SelectMultiVectorLutiLane(Node, 4, Opc, 3);
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return;
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}
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case Intrinsic::aarch64_sme_luti4_lane_zt_x4: {
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if (auto Opc = SelectOpcodeFromVT<SelectTypeKind::AnyType>(
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Node->getValueType(0),
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{0, AArch64::LUTI4_4ZTZI_H, AArch64::LUTI4_4ZTZI_S}))
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// Second Immediate must be <= 1:
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SelectMultiVectorLuti(Node, 4, Opc, 1);
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SelectMultiVectorLutiLane(Node, 4, Opc, 1);
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return;
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}
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case Intrinsic::aarch64_sme_luti2_lane_zt_x2: {
@@ -5495,7 +5527,7 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) {
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{AArch64::LUTI2_2ZTZI_B, AArch64::LUTI2_2ZTZI_H,
54965528
AArch64::LUTI2_2ZTZI_S}))
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// Second Immediate must be <= 7:
5498-
SelectMultiVectorLuti(Node, 2, Opc, 7);
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SelectMultiVectorLutiLane(Node, 2, Opc, 7);
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return;
55005532
}
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case Intrinsic::aarch64_sme_luti4_lane_zt_x2: {
@@ -5504,7 +5536,11 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) {
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{AArch64::LUTI4_2ZTZI_B, AArch64::LUTI4_2ZTZI_H,
55055537
AArch64::LUTI4_2ZTZI_S}))
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// Second Immediate must be <= 3:
5507-
SelectMultiVectorLuti(Node, 2, Opc, 3);
5539+
SelectMultiVectorLutiLane(Node, 2, Opc, 3);
5540+
return;
5541+
}
5542+
case Intrinsic::aarch64_sme_luti4_zt_x4: {
5543+
SelectMultiVectorLuti(Node, 4, AArch64::LUTI4_4ZZT2Z);
55085544
return;
55095545
}
55105546
}

‎llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -940,7 +940,7 @@ defm FAMIN_4Z4Z : sme2_fp_sve_destructive_vector_vg4_multi<"famin", 0b0010101>;
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let Predicates = [HasSME2, HasSME_LUTv2] in {
942942
defm MOVT : sme2_movt_zt_to_zt<"movt", 0b0011111>;
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def LUTI4_4ZZT2Z : sme2_luti4_vector_vg4<0b00, 0b00,"luti4">;
943+
def LUTI4_4ZZT2Z : sme2_luti4_vector_vg4<0b00, 0b00,"luti4">;
944944
} //[HasSME2, HasSME_LUTv2]
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946946
let Predicates = [HasSME2p1, HasSME_LUTv2] in {

‎llvm/test/CodeGen/AArch64/sme2-intrinsics-luti4.ll‎

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,17 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -verify-machineinstrs -force-streaming < %s | FileCheck %s
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target triple = "aarch64-linux"
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define {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>} @test_luti4_zt_i8(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1) #0 {
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; CHECK-LABEL: test_luti4_zt_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1
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; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1
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; CHECK-NEXT: luti4 { z0.b - z3.b }, zt0, { z0, z1 }
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; CHECK-NEXT: ret
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%res = call {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 0, <vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1)
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ret {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>} %res
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}
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attributes #0 = { "target-features"="+sme2,+sme-lutv2"}

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