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[RISCV] Use GPRMemZeroOffset instead of GPRMem in RISCVInstrInfoVPseudos.td. NFC
The distinction between GPRMem and GPRMemZeroOffset only matters for parsing which doesn't apply to pseudos.
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‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 28 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -783,7 +783,7 @@ class VPseudoUSLoadNoMask<VReg RetClass,
783783
int EEW,
784784
DAGOperand sewop = sew> :
785785
Pseudo<(outs RetClass:$rd),
786-
(ins RetClass:$dest, GPRMem:$rs1, AVL:$vl, sewop:$sew,
786+
(ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$vl, sewop:$sew,
787787
vec_policy:$policy), []>,
788788
RISCVVPseudo,
789789
RISCVVLE</*Masked*/0, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
@@ -800,7 +800,7 @@ class VPseudoUSLoadMask<VReg RetClass,
800800
int EEW> :
801801
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
802802
(ins GetVRegNoV0<RetClass>.R:$passthru,
803-
GPRMem:$rs1,
803+
GPRMemZeroOffset:$rs1,
804804
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
805805
RISCVVPseudo,
806806
RISCVVLE</*Masked*/1, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
@@ -818,7 +818,7 @@ class VPseudoUSLoadMask<VReg RetClass,
818818
class VPseudoUSLoadFFNoMask<VReg RetClass,
819819
int EEW> :
820820
Pseudo<(outs RetClass:$rd, GPR:$vl),
821-
(ins RetClass:$dest, GPRMem:$rs1, AVL:$avl,
821+
(ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$avl,
822822
sew:$sew, vec_policy:$policy), []>,
823823
RISCVVPseudo,
824824
RISCVVLE</*Masked*/0, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
@@ -835,7 +835,7 @@ class VPseudoUSLoadFFMask<VReg RetClass,
835835
int EEW> :
836836
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd, GPR:$vl),
837837
(ins GetVRegNoV0<RetClass>.R:$passthru,
838-
GPRMem:$rs1,
838+
GPRMemZeroOffset:$rs1,
839839
VMaskOp:$vm, AVL:$avl, sew:$sew, vec_policy:$policy), []>,
840840
RISCVVPseudo,
841841
RISCVVLE</*Masked*/1, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
@@ -853,7 +853,7 @@ class VPseudoUSLoadFFMask<VReg RetClass,
853853
class VPseudoSLoadNoMask<VReg RetClass,
854854
int EEW> :
855855
Pseudo<(outs RetClass:$rd),
856-
(ins RetClass:$dest, GPRMem:$rs1, GPR:$rs2, AVL:$vl,
856+
(ins RetClass:$dest, GPRMemZeroOffset:$rs1, GPR:$rs2, AVL:$vl,
857857
sew:$sew, vec_policy:$policy), []>,
858858
RISCVVPseudo,
859859
RISCVVLE</*Masked*/0, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
@@ -870,7 +870,7 @@ class VPseudoSLoadMask<VReg RetClass,
870870
int EEW> :
871871
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
872872
(ins GetVRegNoV0<RetClass>.R:$passthru,
873-
GPRMem:$rs1, GPR:$rs2,
873+
GPRMemZeroOffset:$rs1, GPR:$rs2,
874874
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
875875
RISCVVPseudo,
876876
RISCVVLE</*Masked*/1, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
@@ -893,7 +893,7 @@ class VPseudoILoadNoMask<VReg RetClass,
893893
bit EarlyClobber,
894894
bits<2> TargetConstraintType = 1> :
895895
Pseudo<(outs RetClass:$rd),
896-
(ins RetClass:$dest, GPRMem:$rs1, IdxClass:$rs2, AVL:$vl,
896+
(ins RetClass:$dest, GPRMemZeroOffset:$rs1, IdxClass:$rs2, AVL:$vl,
897897
sew:$sew, vec_policy:$policy), []>,
898898
RISCVVPseudo,
899899
RISCVVLX</*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
@@ -916,7 +916,7 @@ class VPseudoILoadMask<VReg RetClass,
916916
bits<2> TargetConstraintType = 1> :
917917
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
918918
(ins GetVRegNoV0<RetClass>.R:$passthru,
919-
GPRMem:$rs1, IdxClass:$rs2,
919+
GPRMemZeroOffset:$rs1, IdxClass:$rs2,
920920
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
921921
RISCVVPseudo,
922922
RISCVVLX</*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
@@ -936,7 +936,7 @@ class VPseudoUSStoreNoMask<VReg StClass,
936936
int EEW,
937937
DAGOperand sewop = sew> :
938938
Pseudo<(outs),
939-
(ins StClass:$rd, GPRMem:$rs1, AVL:$vl, sewop:$sew), []>,
939+
(ins StClass:$rd, GPRMemZeroOffset:$rs1, AVL:$vl, sewop:$sew), []>,
940940
RISCVVPseudo,
941941
RISCVVSE</*Masked*/0, /*Strided*/0, !logtwo(EEW), VLMul> {
942942
let mayLoad = 0;
@@ -949,7 +949,7 @@ class VPseudoUSStoreNoMask<VReg StClass,
949949
class VPseudoUSStoreMask<VReg StClass,
950950
int EEW> :
951951
Pseudo<(outs),
952-
(ins StClass:$rd, GPRMem:$rs1,
952+
(ins StClass:$rd, GPRMemZeroOffset:$rs1,
953953
VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
954954
RISCVVPseudo,
955955
RISCVVSE</*Masked*/1, /*Strided*/0, !logtwo(EEW), VLMul> {
@@ -964,7 +964,7 @@ class VPseudoUSStoreMask<VReg StClass,
964964
class VPseudoSStoreNoMask<VReg StClass,
965965
int EEW> :
966966
Pseudo<(outs),
967-
(ins StClass:$rd, GPRMem:$rs1, GPR:$rs2,
967+
(ins StClass:$rd, GPRMemZeroOffset:$rs1, GPR:$rs2,
968968
AVL:$vl, sew:$sew), []>,
969969
RISCVVPseudo,
970970
RISCVVSE</*Masked*/0, /*Strided*/1, !logtwo(EEW), VLMul> {
@@ -978,7 +978,7 @@ class VPseudoSStoreNoMask<VReg StClass,
978978
class VPseudoSStoreMask<VReg StClass,
979979
int EEW> :
980980
Pseudo<(outs),
981-
(ins StClass:$rd, GPRMem:$rs1, GPR:$rs2,
981+
(ins StClass:$rd, GPRMemZeroOffset:$rs1, GPR:$rs2,
982982
VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
983983
RISCVVPseudo,
984984
RISCVVSE</*Masked*/1, /*Strided*/1, !logtwo(EEW), VLMul> {
@@ -1329,7 +1329,7 @@ class VPseudoTiedBinaryNoMaskRoundingMode<VReg RetClass,
13291329
class VPseudoIStoreNoMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
13301330
bit Ordered>:
13311331
Pseudo<(outs),
1332-
(ins StClass:$rd, GPRMem:$rs1, IdxClass:$rs2, AVL:$vl,
1332+
(ins StClass:$rd, GPRMemZeroOffset:$rs1, IdxClass:$rs2, AVL:$vl,
13331333
sew:$sew),[]>,
13341334
RISCVVPseudo,
13351335
RISCVVSX</*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
@@ -1343,7 +1343,7 @@ class VPseudoIStoreNoMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
13431343
class VPseudoIStoreMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
13441344
bit Ordered>:
13451345
Pseudo<(outs),
1346-
(ins StClass:$rd, GPRMem:$rs1, IdxClass:$rs2,
1346+
(ins StClass:$rd, GPRMemZeroOffset:$rs1, IdxClass:$rs2,
13471347
VMaskOp:$vm, AVL:$vl, sew:$sew),[]>,
13481348
RISCVVPseudo,
13491349
RISCVVSX</*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
@@ -1598,7 +1598,7 @@ class VPseudoUSSegLoadNoMask<VReg RetClass,
15981598
int EEW,
15991599
bits<4> NF> :
16001600
Pseudo<(outs RetClass:$rd),
1601-
(ins RetClass:$dest, GPRMem:$rs1, AVL:$vl,
1601+
(ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$vl,
16021602
sew:$sew, vec_policy:$policy), []>,
16031603
RISCVVPseudo,
16041604
RISCVVLSEG<NF, /*Masked*/0, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
@@ -1615,7 +1615,7 @@ class VPseudoUSSegLoadMask<VReg RetClass,
16151615
int EEW,
16161616
bits<4> NF> :
16171617
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
1618-
(ins GetVRegNoV0<RetClass>.R:$passthru, GPRMem:$rs1,
1618+
(ins GetVRegNoV0<RetClass>.R:$passthru, GPRMemZeroOffset:$rs1,
16191619
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
16201620
RISCVVPseudo,
16211621
RISCVVLSEG<NF, /*Masked*/1, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
@@ -1634,7 +1634,7 @@ class VPseudoUSSegLoadFFNoMask<VReg RetClass,
16341634
int EEW,
16351635
bits<4> NF> :
16361636
Pseudo<(outs RetClass:$rd, GPR:$vl),
1637-
(ins RetClass:$dest, GPRMem:$rs1, AVL:$avl,
1637+
(ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$avl,
16381638
sew:$sew, vec_policy:$policy), []>,
16391639
RISCVVPseudo,
16401640
RISCVVLSEG<NF, /*Masked*/0, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
@@ -1651,7 +1651,7 @@ class VPseudoUSSegLoadFFMask<VReg RetClass,
16511651
int EEW,
16521652
bits<4> NF> :
16531653
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd, GPR:$vl),
1654-
(ins GetVRegNoV0<RetClass>.R:$passthru, GPRMem:$rs1,
1654+
(ins GetVRegNoV0<RetClass>.R:$passthru, GPRMemZeroOffset:$rs1,
16551655
VMaskOp:$vm, AVL:$avl, sew:$sew, vec_policy:$policy), []>,
16561656
RISCVVPseudo,
16571657
RISCVVLSEG<NF, /*Masked*/1, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
@@ -1670,7 +1670,7 @@ class VPseudoSSegLoadNoMask<VReg RetClass,
16701670
int EEW,
16711671
bits<4> NF> :
16721672
Pseudo<(outs RetClass:$rd),
1673-
(ins RetClass:$passthru, GPRMem:$rs1, GPR:$offset, AVL:$vl,
1673+
(ins RetClass:$passthru, GPRMemZeroOffset:$rs1, GPR:$offset, AVL:$vl,
16741674
sew:$sew, vec_policy:$policy), []>,
16751675
RISCVVPseudo,
16761676
RISCVVLSEG<NF, /*Masked*/0, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
@@ -1687,7 +1687,7 @@ class VPseudoSSegLoadMask<VReg RetClass,
16871687
int EEW,
16881688
bits<4> NF> :
16891689
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
1690-
(ins GetVRegNoV0<RetClass>.R:$passthru, GPRMem:$rs1,
1690+
(ins GetVRegNoV0<RetClass>.R:$passthru, GPRMemZeroOffset:$rs1,
16911691
GPR:$offset, VMaskOp:$vm, AVL:$vl, sew:$sew,
16921692
vec_policy:$policy), []>,
16931693
RISCVVPseudo,
@@ -1710,7 +1710,7 @@ class VPseudoISegLoadNoMask<VReg RetClass,
17101710
bits<4> NF,
17111711
bit Ordered> :
17121712
Pseudo<(outs RetClass:$rd),
1713-
(ins RetClass:$passthru, GPRMem:$rs1, IdxClass:$offset, AVL:$vl,
1713+
(ins RetClass:$passthru, GPRMemZeroOffset:$rs1, IdxClass:$offset, AVL:$vl,
17141714
sew:$sew, vec_policy:$policy), []>,
17151715
RISCVVPseudo,
17161716
RISCVVLXSEG<NF, /*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
@@ -1732,7 +1732,7 @@ class VPseudoISegLoadMask<VReg RetClass,
17321732
bits<4> NF,
17331733
bit Ordered> :
17341734
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
1735-
(ins GetVRegNoV0<RetClass>.R:$passthru, GPRMem:$rs1,
1735+
(ins GetVRegNoV0<RetClass>.R:$passthru, GPRMemZeroOffset:$rs1,
17361736
IdxClass:$offset, VMaskOp:$vm, AVL:$vl, sew:$sew,
17371737
vec_policy:$policy), []>,
17381738
RISCVVPseudo,
@@ -1754,7 +1754,7 @@ class VPseudoUSSegStoreNoMask<VReg ValClass,
17541754
int EEW,
17551755
bits<4> NF> :
17561756
Pseudo<(outs),
1757-
(ins ValClass:$rd, GPRMem:$rs1, AVL:$vl, sew:$sew), []>,
1757+
(ins ValClass:$rd, GPRMemZeroOffset:$rs1, AVL:$vl, sew:$sew), []>,
17581758
RISCVVPseudo,
17591759
RISCVVSSEG<NF, /*Masked*/0, /*Strided*/0, !logtwo(EEW), VLMul> {
17601760
let mayLoad = 0;
@@ -1768,7 +1768,7 @@ class VPseudoUSSegStoreMask<VReg ValClass,
17681768
int EEW,
17691769
bits<4> NF> :
17701770
Pseudo<(outs),
1771-
(ins ValClass:$rd, GPRMem:$rs1,
1771+
(ins ValClass:$rd, GPRMemZeroOffset:$rs1,
17721772
VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
17731773
RISCVVPseudo,
17741774
RISCVVSSEG<NF, /*Masked*/1, /*Strided*/0, !logtwo(EEW), VLMul> {
@@ -1784,7 +1784,7 @@ class VPseudoSSegStoreNoMask<VReg ValClass,
17841784
int EEW,
17851785
bits<4> NF> :
17861786
Pseudo<(outs),
1787-
(ins ValClass:$rd, GPRMem:$rs1, GPR:$offset,
1787+
(ins ValClass:$rd, GPRMemZeroOffset:$rs1, GPR:$offset,
17881788
AVL:$vl, sew:$sew), []>,
17891789
RISCVVPseudo,
17901790
RISCVVSSEG<NF, /*Masked*/0, /*Strided*/1, !logtwo(EEW), VLMul> {
@@ -1799,7 +1799,7 @@ class VPseudoSSegStoreMask<VReg ValClass,
17991799
int EEW,
18001800
bits<4> NF> :
18011801
Pseudo<(outs),
1802-
(ins ValClass:$rd, GPRMem:$rs1, GPR: $offset,
1802+
(ins ValClass:$rd, GPRMemZeroOffset:$rs1, GPR: $offset,
18031803
VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
18041804
RISCVVPseudo,
18051805
RISCVVSSEG<NF, /*Masked*/1, /*Strided*/1, !logtwo(EEW), VLMul> {
@@ -1818,7 +1818,7 @@ class VPseudoISegStoreNoMask<VReg ValClass,
18181818
bits<4> NF,
18191819
bit Ordered> :
18201820
Pseudo<(outs),
1821-
(ins ValClass:$rd, GPRMem:$rs1, IdxClass: $index,
1821+
(ins ValClass:$rd, GPRMemZeroOffset:$rs1, IdxClass: $index,
18221822
AVL:$vl, sew:$sew), []>,
18231823
RISCVVPseudo,
18241824
RISCVVSXSEG<NF, /*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
@@ -1836,7 +1836,7 @@ class VPseudoISegStoreMask<VReg ValClass,
18361836
bits<4> NF,
18371837
bit Ordered> :
18381838
Pseudo<(outs),
1839-
(ins ValClass:$rd, GPRMem:$rs1, IdxClass: $index,
1839+
(ins ValClass:$rd, GPRMemZeroOffset:$rs1, IdxClass: $index,
18401840
VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
18411841
RISCVVPseudo,
18421842
RISCVVSXSEG<NF, /*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {

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