Skip to content

Commit 332645a

Browse files
DragonBluepdangowrt
DragonBluep
authored and
dangowrt
committed
uboot-mediatek: sync with mtk-openwrt/u-boot 20250711
- Backport upstream Winbond W25N04KV Flash support. - Backport upstream GigaDevice series Flash support. - Backport pending Airoha AN8855 switch TPID value fix. - Backport Mediatek UART baudrate accuracy compensation support. - Pull mtk patchset from MTK SDK mtksoc-20250711 branch: Remove mt7622_rfb changes. The MTK SDK already dropped them. Replace Airoha ethernet PHY driver with new version. Split downstream snfi changes into independent patches. Add new Marvell CUX3410 PHY driver. Add new MediaTek built-in 2.5Gbps PHY driver. Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
1 parent bbd3db4 commit 332645a

File tree

42 files changed

+55860
-2647
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

42 files changed

+55860
-2647
lines changed

‎package/boot/uboot-mediatek/patches/001-mtd-spinand-winbond-add-Winbond-W25N04KV-flash-suppo.patch‎

Lines changed: 56 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,56 @@
1+
From fe37fb8214e40ea64cf03453d112527b629fb08a Mon Sep 17 00:00:00 2001
2+
From: Christian Marangi <ansuelsmth@gmail.com>
3+
Date: Sat, 7 Jun 2025 23:11:21 +0200
4+
Subject: [PATCH] mtd: spinand: winbond: add Winbond W25N04KV flash support
5+
6+
Add Winbond W25N04KV flash support that use a different value to detect
7+
ECC bitflip.
8+
9+
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
10+
---
11+
drivers/mtd/nand/spi/winbond.c | 13 +++++++++++++
12+
1 file changed, 13 insertions(+)
13+
14+
--- a/drivers/mtd/nand/spi/winbond.c
15+
+++ b/drivers/mtd/nand/spi/winbond.c
16+
@@ -11,6 +11,7 @@
17+
#include <linux/device.h>
18+
#include <linux/kernel.h>
19+
#endif
20+
+#include <linux/bitfield.h>
21+
#include <linux/bug.h>
22+
#include <linux/mtd/spinand.h>
23+
24+
@@ -18,6 +19,8 @@
25+
26+
#define WINBOND_CFG_BUF_READ BIT(3)
27+
28+
+#define W25N04KV_STATUS_ECC_5_8_BITFLIPS GENMASK(5, 4)
29+
+
30+
static SPINAND_OP_VARIANTS(read_cache_variants,
31+
SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
32+
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
33+
@@ -121,6 +124,7 @@ static int w25n02kv_ecc_get_status(struc
34+
return -EBADMSG;
35+
36+
case STATUS_ECC_HAS_BITFLIPS:
37+
+ case W25N04KV_STATUS_ECC_5_8_BITFLIPS:
38+
/*
39+
* Let's try to retrieve the real maximum number of bitflips
40+
* in order to avoid forcing the wear-leveling layer to move
41+
@@ -169,6 +173,15 @@ static const struct spinand_info winbond
42+
NAND_ECCREQ(8, 512),
43+
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
44+
&write_cache_variants,
45+
+ &update_cache_variants),
46+
+ 0,
47+
+ SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)),
48+
+ SPINAND_INFO("W25N04KV",
49+
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x23),
50+
+ NAND_MEMORG(1, 2048, 128, 64, 4096, 40, 2, 1, 1),
51+
+ NAND_ECCREQ(8, 512),
52+
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
53+
+ &write_cache_variants,
54+
&update_cache_variants),
55+
0,
56+
SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)),

‎package/boot/uboot-mediatek/patches/002-mtd-spinand-gigadevice-sync-supported-chips-with-lin.patch‎

Lines changed: 245 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,245 @@
1+
From 506ceddffdc40acf709822b678b986e2e22c5056 Mon Sep 17 00:00:00 2001
2+
From: Chuanhong Guo <gch981213@gmail.com>
3+
Date: Wed, 1 May 2024 15:45:23 +0800
4+
Subject: [PATCH] mtd/spinand: gigadevice: sync supported chips with linux 6.9
5+
6+
Adding support for:
7+
GD5F1GQ4RExxG
8+
GD5F2GQ4UExxG
9+
GD5F2GQ4RExxG
10+
GD5F1GQ5RExxG
11+
GD5F2GQ5UExxG
12+
GD5F2GQ5RExxG
13+
GD5F4GQ6UExxG
14+
GD5F4GQ6RExxG
15+
GD5F1GM7UExxG
16+
GD5F1GM7RExxG
17+
GD5F2GM7UExxG
18+
GD5F2GM7RExxG
19+
GD5F4GM8UExxG
20+
GD5F4GM8RExxG
21+
GD5F2GQ5xExxH
22+
GD5F1GQ5RExxH
23+
GD5F1GQ4RExxH
24+
25+
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
26+
---
27+
drivers/mtd/nand/spi/gigadevice.c | 188 +++++++++++++++++++++++++++++-
28+
1 file changed, 187 insertions(+), 1 deletion(-)
29+
30+
--- a/drivers/mtd/nand/spi/gigadevice.c
31+
+++ b/drivers/mtd/nand/spi/gigadevice.c
32+
@@ -43,6 +43,22 @@ static SPINAND_OP_VARIANTS(read_cache_va
33+
SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0),
34+
SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0));
35+
36+
+static SPINAND_OP_VARIANTS(read_cache_variants_1gq5,
37+
+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
38+
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
39+
+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
40+
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
41+
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
42+
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
43+
+
44+
+static SPINAND_OP_VARIANTS(read_cache_variants_2gq5,
45+
+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 4, NULL, 0),
46+
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
47+
+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 2, NULL, 0),
48+
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
49+
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
50+
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
51+
+
52+
static SPINAND_OP_VARIANTS(write_cache_variants,
53+
SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
54+
SPINAND_PROG_LOAD(true, 0, NULL, 0));
55+
@@ -329,6 +345,36 @@ static const struct spinand_info gigadev
56+
SPINAND_HAS_QE_BIT,
57+
SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
58+
gd5fxgq4uexxg_ecc_get_status)),
59+
+ SPINAND_INFO("GD5F1GQ4RExxG",
60+
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc1),
61+
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
62+
+ NAND_ECCREQ(8, 512),
63+
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
64+
+ &write_cache_variants,
65+
+ &update_cache_variants),
66+
+ SPINAND_HAS_QE_BIT,
67+
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
68+
+ gd5fxgq4uexxg_ecc_get_status)),
69+
+ SPINAND_INFO("GD5F2GQ4UExxG",
70+
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd2),
71+
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
72+
+ NAND_ECCREQ(8, 512),
73+
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
74+
+ &write_cache_variants,
75+
+ &update_cache_variants),
76+
+ SPINAND_HAS_QE_BIT,
77+
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
78+
+ gd5fxgq4uexxg_ecc_get_status)),
79+
+ SPINAND_INFO("GD5F2GQ4RExxG",
80+
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc2),
81+
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
82+
+ NAND_ECCREQ(8, 512),
83+
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
84+
+ &write_cache_variants,
85+
+ &update_cache_variants),
86+
+ SPINAND_HAS_QE_BIT,
87+
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
88+
+ gd5fxgq4uexxg_ecc_get_status)),
89+
SPINAND_INFO("GD5F1GQ4UFxxG",
90+
SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb1, 0x48),
91+
NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
92+
@@ -343,12 +389,152 @@ static const struct spinand_info gigadev
93+
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51),
94+
NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
95+
NAND_ECCREQ(4, 512),
96+
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
97+
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
98+
&write_cache_variants,
99+
&update_cache_variants),
100+
SPINAND_HAS_QE_BIT,
101+
SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
102+
gd5fxgq5xexxg_ecc_get_status)),
103+
+ SPINAND_INFO("GD5F1GQ5RExxG",
104+
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x41),
105+
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
106+
+ NAND_ECCREQ(4, 512),
107+
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
108+
+ &write_cache_variants,
109+
+ &update_cache_variants),
110+
+ SPINAND_HAS_QE_BIT,
111+
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
112+
+ gd5fxgq5xexxg_ecc_get_status)),
113+
+ SPINAND_INFO("GD5F2GQ5UExxG",
114+
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x52),
115+
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
116+
+ NAND_ECCREQ(4, 512),
117+
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
118+
+ &write_cache_variants,
119+
+ &update_cache_variants),
120+
+ SPINAND_HAS_QE_BIT,
121+
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
122+
+ gd5fxgq5xexxg_ecc_get_status)),
123+
+ SPINAND_INFO("GD5F2GQ5RExxG",
124+
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x42),
125+
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
126+
+ NAND_ECCREQ(4, 512),
127+
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
128+
+ &write_cache_variants,
129+
+ &update_cache_variants),
130+
+ SPINAND_HAS_QE_BIT,
131+
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
132+
+ gd5fxgq5xexxg_ecc_get_status)),
133+
+ SPINAND_INFO("GD5F4GQ6UExxG",
134+
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x55),
135+
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 2, 1),
136+
+ NAND_ECCREQ(4, 512),
137+
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
138+
+ &write_cache_variants,
139+
+ &update_cache_variants),
140+
+ SPINAND_HAS_QE_BIT,
141+
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
142+
+ gd5fxgq5xexxg_ecc_get_status)),
143+
+ SPINAND_INFO("GD5F4GQ6RExxG",
144+
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x45),
145+
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 2, 1),
146+
+ NAND_ECCREQ(4, 512),
147+
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
148+
+ &write_cache_variants,
149+
+ &update_cache_variants),
150+
+ SPINAND_HAS_QE_BIT,
151+
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
152+
+ gd5fxgq5xexxg_ecc_get_status)),
153+
+ SPINAND_INFO("GD5F1GM7UExxG",
154+
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x91),
155+
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
156+
+ NAND_ECCREQ(8, 512),
157+
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
158+
+ &write_cache_variants,
159+
+ &update_cache_variants),
160+
+ SPINAND_HAS_QE_BIT,
161+
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
162+
+ gd5fxgq4uexxg_ecc_get_status)),
163+
+ SPINAND_INFO("GD5F1GM7RExxG",
164+
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x81),
165+
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
166+
+ NAND_ECCREQ(8, 512),
167+
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
168+
+ &write_cache_variants,
169+
+ &update_cache_variants),
170+
+ SPINAND_HAS_QE_BIT,
171+
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
172+
+ gd5fxgq4uexxg_ecc_get_status)),
173+
+ SPINAND_INFO("GD5F2GM7UExxG",
174+
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x92),
175+
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
176+
+ NAND_ECCREQ(8, 512),
177+
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
178+
+ &write_cache_variants,
179+
+ &update_cache_variants),
180+
+ SPINAND_HAS_QE_BIT,
181+
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
182+
+ gd5fxgq4uexxg_ecc_get_status)),
183+
+ SPINAND_INFO("GD5F2GM7RExxG",
184+
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x82),
185+
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
186+
+ NAND_ECCREQ(8, 512),
187+
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
188+
+ &write_cache_variants,
189+
+ &update_cache_variants),
190+
+ SPINAND_HAS_QE_BIT,
191+
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
192+
+ gd5fxgq4uexxg_ecc_get_status)),
193+
+ SPINAND_INFO("GD5F4GM8UExxG",
194+
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x95),
195+
+ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
196+
+ NAND_ECCREQ(8, 512),
197+
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
198+
+ &write_cache_variants,
199+
+ &update_cache_variants),
200+
+ SPINAND_HAS_QE_BIT,
201+
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
202+
+ gd5fxgq4uexxg_ecc_get_status)),
203+
+ SPINAND_INFO("GD5F4GM8RExxG",
204+
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x85),
205+
+ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
206+
+ NAND_ECCREQ(8, 512),
207+
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
208+
+ &write_cache_variants,
209+
+ &update_cache_variants),
210+
+ SPINAND_HAS_QE_BIT,
211+
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
212+
+ gd5fxgq4uexxg_ecc_get_status)),
213+
+ SPINAND_INFO("GD5F2GQ5xExxH",
214+
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x22),
215+
+ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
216+
+ NAND_ECCREQ(4, 512),
217+
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
218+
+ &write_cache_variants,
219+
+ &update_cache_variants),
220+
+ SPINAND_HAS_QE_BIT,
221+
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
222+
+ gd5fxgq4uexxg_ecc_get_status)),
223+
+ SPINAND_INFO("GD5F1GQ5RExxH",
224+
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x21),
225+
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
226+
+ NAND_ECCREQ(4, 512),
227+
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
228+
+ &write_cache_variants,
229+
+ &update_cache_variants),
230+
+ SPINAND_HAS_QE_BIT,
231+
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
232+
+ gd5fxgq4uexxg_ecc_get_status)),
233+
+ SPINAND_INFO("GD5F1GQ4RExxH",
234+
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xc9),
235+
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
236+
+ NAND_ECCREQ(4, 512),
237+
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
238+
+ &write_cache_variants,
239+
+ &update_cache_variants),
240+
+ SPINAND_HAS_QE_BIT,
241+
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
242+
+ gd5fxgq4uexxg_ecc_get_status)),
243+
};
244+
245+
static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {

‎package/boot/uboot-mediatek/patches/003-net-mediatek-correct-the-AN8855-TPID-value-in-port-i.patch‎

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
1+
From dc495442ba610b190775122a31f958ad74229262 Mon Sep 17 00:00:00 2001
2+
From: Weijie Gao <weijie.gao@mediatek.com>
3+
Date: Tue, 8 Jul 2025 17:53:48 +0800
4+
Subject: [PATCH] net: mediatek: correct the AN8855 TPID value in port
5+
isolation settings
6+
7+
The TPID value should be 0x9100 instead of 0x8100 according to the
8+
datasheet.
9+
10+
Fixes: cedafee9ff3 (net: mediatek: add support for Airoha AN8855 ethernet switch)
11+
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
12+
---
13+
drivers/net/mtk_eth/an8855.c | 2 +-
14+
1 file changed, 1 insertion(+), 1 deletion(-)
15+
16+
--- a/drivers/net/mtk_eth/an8855.c
17+
+++ b/drivers/net/mtk_eth/an8855.c
18+
@@ -909,7 +909,7 @@ static void an8855_port_isolation(struct
19+
20+
/* Set port mode to user port */
21+
an8855_reg_write(priv, AN8855_PVC(i),
22+
- (0x8100 << AN8855_STAG_VPID_S) |
23+
+ (0x9100 << AN8855_STAG_VPID_S) |
24+
(VLAN_ATTR_USER << AN8855_VLAN_ATTR_S));
25+
}
26+
}

‎package/boot/uboot-mediatek/patches/004-01-serial-mediatek-fix-register-names-and-offsets.patch‎

Lines changed: 44 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,44 @@
1+
From 6e15d3f91aa698798578d39a6d9e292fcc5c577f Mon Sep 17 00:00:00 2001
2+
From: Weijie Gao <weijie.gao@mediatek.com>
3+
Date: Fri, 23 May 2025 17:25:55 +0800
4+
Subject: [PATCH] serial: mediatek: fix register names and offsets
5+
6+
Fix UART register names and offsets according to the programming
7+
guide to allow implementing some enhanced features.
8+
9+
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
10+
---
11+
drivers/serial/serial_mtk.c | 17 ++++++++++++-----
12+
1 file changed, 12 insertions(+), 5 deletions(-)
13+
14+
--- a/drivers/serial/serial_mtk.c
15+
+++ b/drivers/serial/serial_mtk.c
16+
@@ -30,16 +30,23 @@ struct mtk_serial_regs {
17+
u32 mcr;
18+
u32 lsr;
19+
u32 msr;
20+
- u32 spr;
21+
- u32 mdr1;
22+
+ u32 scr;
23+
+ u32 autobaud_en;
24+
u32 highspeed;
25+
u32 sample_count;
26+
u32 sample_point;
27+
+ u32 autobaud_reg;
28+
+ u32 ratefix_ad;
29+
+ u32 autobaud_sample;
30+
+ u32 guard;
31+
+ u32 escape_dat;
32+
+ u32 escape_en;
33+
+ u32 sleep_en;
34+
+ u32 dma_en;
35+
+ u32 rxtri_ad;
36+
u32 fracdiv_l;
37+
u32 fracdiv_m;
38+
- u32 escape_en;
39+
- u32 guard;
40+
- u32 rx_sel;
41+
+ u32 fcr_rd;
42+
};
43+
44+
#define thr rbr

0 commit comments

Comments
 (0)