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DragonBluephauke
DragonBluep
authored and
hauke
committed
ramips: sync upstream Ralink clock patches
1. Add sdhc clock for MT7620 and MT76x8 SoCs. 2. Fix clock driver warning for RT2880, RT305x and RT3883. Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Shiji Yang <[email protected]> Link: openwrt/openwrt#17037 Signed-off-by: Hauke Mehrtens <[email protected]>
1 parent eb39558 commit 7bb99bc

7 files changed

+269
-55
lines changed

‎target/linux/ramips/dts/mt7620a.dtsi‎

Lines changed: 10 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -32,13 +32,6 @@
3232
compatible = "mti,cpu-interrupt-controller";
3333
};
3434

35-
mmc_clk: mmc-clock {
36-
compatible = "fixed-clock";
37-
#clock-cells = <0>;
38-
clock-frequency = <48000000>;
39-
clock-accuracy = <100>;
40-
};
41-
4235
mmc_reg_1v8: regulator-1v8 {
4336
compatible = "regulator-fixed";
4437

@@ -80,7 +73,7 @@
8073
compatible = "ralink,rt2880-timer";
8174
reg = <0x100 0x20>;
8275

83-
clocks = <&sysc 5>;
76+
clocks = <&sysc 7>;
8477

8578
interrupt-parent = <&intc>;
8679
interrupts = <1>;
@@ -90,7 +83,7 @@
9083
compatible = "ralink,rt2880-wdt";
9184
reg = <0x120 0x10>;
9285

93-
clocks = <&sysc 6>;
86+
clocks = <&sysc 8>;
9487

9588
resets = <&sysc 8>;
9689
reset-names = "wdt";
@@ -122,7 +115,7 @@
122115
compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
123116
reg = <0x500 0x100>;
124117

125-
clocks = <&sysc 7>;
118+
clocks = <&sysc 9>;
126119

127120
resets = <&sysc 12>;
128121

@@ -216,7 +209,7 @@
216209
compatible = "ralink,rt2880-i2c";
217210
reg = <0x900 0x100>;
218211

219-
clocks = <&sysc 8>;
212+
clocks = <&sysc 10>;
220213

221214
resets = <&sysc 16>;
222215
reset-names = "i2c";
@@ -234,7 +227,7 @@
234227
compatible = "mediatek,mt7620-i2s";
235228
reg = <0xa00 0x100>;
236229

237-
clocks = <&sysc 9>;
230+
clocks = <&sysc 11>;
238231

239232
resets = <&sysc 17>;
240233
reset-names = "i2s";
@@ -256,7 +249,7 @@
256249
compatible = "ralink,rt2880-spi";
257250
reg = <0xb00 0x40>;
258251

259-
clocks = <&sysc 10>;
252+
clocks = <&sysc 12>;
260253

261254
resets = <&sysc 18>;
262255
reset-names = "spi";
@@ -274,7 +267,7 @@
274267
compatible = "ralink,rt2880-spi";
275268
reg = <0xb40 0x60>;
276269

277-
clocks = <&sysc 11>;
270+
clocks = <&sysc 13>;
278271

279272
resets = <&sysc 18>;
280273
reset-names = "spi";
@@ -292,7 +285,7 @@
292285
compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
293286
reg = <0xc00 0x100>;
294287

295-
clocks = <&sysc 12>;
288+
clocks = <&sysc 14>;
296289

297290
resets = <&sysc 19>;
298291

@@ -539,7 +532,7 @@
539532
cap-mmc-highspeed;
540533
cap-sd-highspeed;
541534

542-
clocks = <&mmc_clk>, <&mmc_clk>;
535+
clocks = <&sysc 15>, <&sysc 15>;
543536
clock-names = "source", "hclk";
544537

545538
disable-wp;
@@ -645,7 +638,7 @@
645638
compatible = "ralink,rt7620-wmac", "ralink,rt2880-wmac";
646639
reg = <0x10180000 0x40000>;
647640

648-
clocks = <&sysc 13>;
641+
clocks = <&sysc 16>;
649642

650643
interrupt-parent = <&cpuintc>;
651644
interrupts = <6>;

‎target/linux/ramips/dts/mt7620n.dtsi‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,7 @@
5151
compatible = "ralink,rt2880-timer";
5252
reg = <0x100 0x20>;
5353

54-
clocks = <&sysc 5>;
54+
clocks = <&sysc 7>;
5555

5656
interrupt-parent = <&intc>;
5757
interrupts = <1>;
@@ -61,7 +61,7 @@
6161
compatible = "ralink,rt2880-wdt";
6262
reg = <0x120 0x10>;
6363

64-
clocks = <&sysc 6>;
64+
clocks = <&sysc 8>;
6565

6666
resets = <&sysc 8>;
6767
reset-names = "wdt";
@@ -171,7 +171,7 @@
171171
compatible = "ralink,rt2880-i2c";
172172
reg = <0x900 0x100>;
173173

174-
clocks = <&sysc 8>;
174+
clocks = <&sysc 10>;
175175

176176
resets = <&sysc 16>;
177177
reset-names = "i2c";
@@ -189,7 +189,7 @@
189189
compatible = "ralink,rt2880-spi";
190190
reg = <0xb00 0x40>;
191191

192-
clocks = <&sysc 10>;
192+
clocks = <&sysc 12>;
193193

194194
resets = <&sysc 18>;
195195
reset-names = "spi";
@@ -207,7 +207,7 @@
207207
compatible = "ralink,rt2880-spi";
208208
reg = <0xb40 0x60>;
209209

210-
clocks = <&sysc 11>;
210+
clocks = <&sysc 13>;
211211

212212
resets = <&sysc 18>;
213213
reset-names = "spi";
@@ -225,7 +225,7 @@
225225
compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
226226
reg = <0xc00 0x100>;
227227

228-
clocks = <&sysc 12>;
228+
clocks = <&sysc 14>;
229229

230230
resets = <&sysc 19>;
231231

@@ -372,7 +372,7 @@
372372
compatible = "ralink,rt7620-wmac", "ralink,rt2880-wmac";
373373
reg = <0x10180000 0x40000>;
374374

375-
clocks = <&sysc 13>;
375+
clocks = <&sysc 16>;
376376

377377
interrupt-parent = <&cpuintc>;
378378
interrupts = <6>;

‎target/linux/ramips/dts/mt7628an.dtsi‎

Lines changed: 8 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -30,13 +30,6 @@
3030
compatible = "mti,cpu-interrupt-controller";
3131
};
3232

33-
mmc_clk: mmc-clock {
34-
compatible = "fixed-clock";
35-
#clock-cells = <0>;
36-
clock-frequency = <48000000>;
37-
clock-accuracy = <100>;
38-
};
39-
4033
mmc_reg_1v8: regulator-1v8 {
4134
compatible = "regulator-fixed";
4235

@@ -121,7 +114,7 @@
121114
compatible = "mediatek,mt7621-i2c";
122115
reg = <0x900 0x100>;
123116

124-
clocks = <&sysc 7>;
117+
clocks = <&sysc 9>;
125118
clock-names = "i2c";
126119

127120
resets = <&sysc 16>;
@@ -140,7 +133,7 @@
140133
compatible = "mediatek,mt7628-i2s";
141134
reg = <0xa00 0x100>;
142135

143-
clocks = <&sysc 8>;
136+
clocks = <&sysc 10>;
144137

145138
resets = <&sysc 17>;
146139
reset-names = "i2s";
@@ -162,7 +155,7 @@
162155
compatible = "ralink,mt7621-spi";
163156
reg = <0xb00 0x100>;
164157

165-
clocks = <&sysc 9>;
158+
clocks = <&sysc 11>;
166159
clock-names = "spi";
167160

168161
resets = <&sysc 18>;
@@ -185,7 +178,7 @@
185178
reg-io-width = <4>;
186179
no-loopback-test;
187180

188-
clocks = <&sysc 11>;
181+
clocks = <&sysc 13>;
189182

190183
resets = <&sysc 12>;
191184

@@ -204,7 +197,7 @@
204197
reg-io-width = <4>;
205198
no-loopback-test;
206199

207-
clocks = <&sysc 12>;
200+
clocks = <&sysc 14>;
208201

209202
resets = <&sysc 19>;
210203

@@ -225,7 +218,7 @@
225218
reg-io-width = <4>;
226219
no-loopback-test;
227220

228-
clocks = <&sysc 13>;
221+
clocks = <&sysc 15>;
229222

230223
resets = <&sysc 20>;
231224

@@ -393,7 +386,7 @@
393386
cap-mmc-highspeed;
394387
cap-sd-highspeed;
395388

396-
clocks = <&mmc_clk>, <&mmc_clk>;
389+
clocks = <&sysc 16>, <&sysc 16>;
397390
clock-names = "source", "hclk";
398391

399392
disable-wp;
@@ -516,7 +509,7 @@
516509
compatible = "mediatek,mt7628-wmac";
517510
reg = <0x10300000 0x100000>;
518511

519-
clocks = <&sysc 14>;
512+
clocks = <&sysc 17>;
520513

521514
interrupt-parent = <&cpuintc>;
522515
interrupts = <6>;

‎target/linux/ramips/dts/rt3883.dtsi‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,7 @@
5151
compatible = "ralink,rt2880-timer";
5252
reg = <0x100 0x20>;
5353

54-
clocks = <&sysc 4>;
54+
clocks = <&sysc 5>;
5555

5656
interrupt-parent = <&intc>;
5757
interrupts = <1>;
@@ -61,7 +61,7 @@
6161
compatible = "ralink,rt2880-wdt";
6262
reg = <0x120 0x10>;
6363

64-
clocks = <&sysc 5>;
64+
clocks = <&sysc 6>;
6565

6666
resets = <&sysc 8>;
6767
reset-names = "wdt";
@@ -93,7 +93,7 @@
9393
compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
9494
reg = <0x500 0x100>;
9595

96-
clocks = <&sysc 6>;
96+
clocks = <&sysc 7>;
9797

9898
resets = <&sysc 12>;
9999

@@ -187,7 +187,7 @@
187187
compatible = "ralink,rt2880-i2c";
188188
reg = <0x900 0x100>;
189189

190-
clocks = <&sysc 7>;
190+
clocks = <&sysc 8>;
191191

192192
resets = <&sysc 16>;
193193
reset-names = "i2c";
@@ -205,7 +205,7 @@
205205
compatible = "ralink,rt3883-i2s";
206206
reg = <0xa00 0x100>;
207207

208-
clocks = <&sysc 8>;
208+
clocks = <&sysc 9>;
209209

210210
resets = <&sysc 17>;
211211
reset-names = "i2s";
@@ -229,7 +229,7 @@
229229
#address-cells = <1>;
230230
#size-cells = <0>;
231231

232-
clocks = <&sysc 9>;
232+
clocks = <&sysc 10>;
233233

234234
resets = <&sysc 18>;
235235
reset-names = "spi";
@@ -246,7 +246,7 @@
246246
#address-cells = <1>;
247247
#size-cells = <0>;
248248

249-
clocks = <&sysc 10>;
249+
clocks = <&sysc 11>;
250250

251251
resets = <&sysc 18>;
252252
reset-names = "spi";
@@ -261,7 +261,7 @@
261261
compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
262262
reg = <0xc00 0x100>;
263263

264-
clocks = <&sysc 11>;
264+
clocks = <&sysc 12>;
265265

266266
resets = <&sysc 19>;
267267

@@ -343,7 +343,7 @@
343343
#size-cells = <0>;
344344
reg = <0x10100000 0x10000>;
345345

346-
clocks = <&sysc 12>;
346+
clocks = <&sysc 13>;
347347

348348
resets = <&sysc 21>;
349349
reset-names = "fe";
@@ -463,7 +463,7 @@
463463
compatible = "ralink,rt3883-wmac", "ralink,rt2880-wmac";
464464
reg = <0x10180000 0x40000>;
465465

466-
clocks = <&sysc 13>;
466+
clocks = <&sysc 14>;
467467

468468
interrupt-parent = <&cpuintc>;
469469
interrupts = <6>;

target/linux/ramips/patches-6.6/100-clk-ralink-mtmips-fix-clock-plan-for-Ralink-SoC-RT3883.patch renamed to target/linux/ramips/patches-6.6/002-01-v6.13-clk-ralink-mtmips-fix-clock-plan-for-Ralink-SoC-RT38.patch

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
1-
Subject: [PATCH] clk: ralink: mtmips: fix clock plan for Ralink SoC RT3883
2-
Date: Tue, 6 Aug 2024 16:29:02 +0200
3-
Message-Id: <[email protected]>
1+
From 33239152305567b3e9bf052f71fd4baecd626341 Mon Sep 17 00:00:00 2001
2+
From: Sergio Paracuellos <[email protected]>
3+
Date: Tue, 10 Sep 2024 06:40:22 +0200
4+
Subject: [PATCH 1/3] clk: ralink: mtmips: fix clock plan for Ralink SoC RT3883
45

56
Clock plan for Ralink SoC RT3883 needs an extra 'periph' clock to properly
67
set some peripherals that has this clock as their parent. When this driver
@@ -14,6 +15,8 @@ properly working clock plan for this SoC.
1415

1516
Fixes: 6f3b15586eef ("clk: ralink: add clock and reset driver for MTMIPS SoCs")
1617
Signed-off-by: Sergio Paracuellos <[email protected]>
18+
Link: https://lore.kernel.org/r/[email protected]
19+
Signed-off-by: Stephen Boyd <[email protected]>
1720
---
1821
drivers/clk/ralink/clk-mtmips.c | 9 +++++++--
1922
1 file changed, 7 insertions(+), 2 deletions(-)
@@ -24,7 +27,7 @@ Signed-off-by: Sergio Paracuellos <[email protected]>
2427
CLK_FIXED("xtal", NULL, 40000000)
2528
};
2629

27-
+static struct mtmips_clk_fixed rt3383_fixed_clocks[] = {
30+
+static struct mtmips_clk_fixed rt3883_fixed_clocks[] = {
2831
+ CLK_FIXED("xtal", NULL, 40000000),
2932
+ CLK_FIXED("periph", "xtal", 40000000)
3033
+};
@@ -38,8 +41,8 @@ Signed-off-by: Sergio Paracuellos <[email protected]>
3841
.num_clk_base = ARRAY_SIZE(rt3883_clks_base),
3942
- .clk_fixed = rt305x_fixed_clocks,
4043
- .num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks),
41-
+ .clk_fixed = rt3383_fixed_clocks,
42-
+ .num_clk_fixed = ARRAY_SIZE(rt3383_fixed_clocks),
44+
+ .clk_fixed = rt3883_fixed_clocks,
45+
+ .num_clk_fixed = ARRAY_SIZE(rt3883_fixed_clocks),
4346
.clk_factor = NULL,
4447
.num_clk_factor = 0,
4548
.clk_periph = rt5350_pherip_clks,

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