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plappermaulhauke
plappermaul
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hauke
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realtek: dsa: relax capability checks for 2.5G modes
The driver currently uses two checks to verify the capabilities. These are ..._phylink_get_caps() and ..._pcs_validate(). For RTL930x these must allow 2.5G modes. Enhance that as follows: Add 2500BASEX to phylink_get_caps(). Sort the interfaces alphabetically and rename the function to the new prefix. IMPORTANT REMARK! Until now this function allowed the XGMII mode (10G only parallel interface) that was somehow mixed with the Realtek proprietary mode XSGMII (10G SGMII). Remove it to avoid further confusion. Looking upstream pcs_validate() is used less and less. There are only 2 consumers left in 6.16 and the calling location reads: /* Validate the link parameters with the PCS */ if (pcs->ops->pcs_validate) { ret = pcs->ops->pcs_validate(pcs, supported, state); if (ret < 0 || phylink_is_empty_linkmode(supported)) return -EINVAL; /* Ensure the advertising mask is a subset of the * supported mask. */ linkmode_and(state->advertising, state->advertising, supported); } There is no need for this additional check. Drop the functions. Tested-by: Jan Hoffmann <jan@3e8.eu> Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> Link: openwrt/openwrt#19429 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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  • target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx

1 file changed

+7
-155
lines changed

‎target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/dsa.c‎

Lines changed: 7 additions & 155 deletions
Original file line numberDiff line numberDiff line change
@@ -340,152 +340,6 @@ static int rtl93xx_get_sds(struct phy_device *phydev)
340340
return sds_num;
341341
}
342342

343-
static int rtl83xx_pcs_validate(struct phylink_pcs *pcs,
344-
unsigned long *supported,
345-
const struct phylink_link_state *state)
346-
{
347-
struct rtl838x_pcs *rtpcs = container_of(pcs, struct rtl838x_pcs, pcs);
348-
struct rtl838x_switch_priv *priv = rtpcs->priv;
349-
int port = rtpcs->port;
350-
__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
351-
352-
pr_debug("In %s port %d, state is %d", __func__, port, state->interface);
353-
354-
if (!phy_interface_mode_is_rgmii(state->interface) &&
355-
state->interface != PHY_INTERFACE_MODE_NA &&
356-
state->interface != PHY_INTERFACE_MODE_1000BASEX &&
357-
state->interface != PHY_INTERFACE_MODE_MII &&
358-
state->interface != PHY_INTERFACE_MODE_REVMII &&
359-
state->interface != PHY_INTERFACE_MODE_GMII &&
360-
state->interface != PHY_INTERFACE_MODE_QSGMII &&
361-
state->interface != PHY_INTERFACE_MODE_INTERNAL &&
362-
state->interface != PHY_INTERFACE_MODE_SGMII) {
363-
bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
364-
dev_err(priv->ds->dev,
365-
"Unsupported interface: %d for port %d\n",
366-
state->interface, port);
367-
return -EINVAL;
368-
}
369-
370-
/* Allow all the expected bits */
371-
phylink_set(mask, Autoneg);
372-
phylink_set_port_modes(mask);
373-
phylink_set(mask, Pause);
374-
phylink_set(mask, Asym_Pause);
375-
376-
/* With the exclusion of MII and Reverse MII, we support Gigabit,
377-
* including Half duplex
378-
*/
379-
if (state->interface != PHY_INTERFACE_MODE_MII &&
380-
state->interface != PHY_INTERFACE_MODE_REVMII) {
381-
phylink_set(mask, 1000baseT_Full);
382-
phylink_set(mask, 1000baseT_Half);
383-
}
384-
385-
/* On both the 8380 and 8382, ports 24-27 are SFP ports */
386-
if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)
387-
phylink_set(mask, 1000baseX_Full);
388-
389-
/* On the RTL839x family of SoCs, ports 48 to 51 are SFP ports */
390-
if (port >= 48 && port <= 51 && priv->family_id == RTL8390_FAMILY_ID)
391-
phylink_set(mask, 1000baseX_Full);
392-
393-
phylink_set(mask, 10baseT_Half);
394-
phylink_set(mask, 10baseT_Full);
395-
phylink_set(mask, 100baseT_Half);
396-
phylink_set(mask, 100baseT_Full);
397-
398-
bitmap_and(supported, supported, mask,
399-
__ETHTOOL_LINK_MODE_MASK_NBITS);
400-
401-
return 0;
402-
}
403-
404-
static int rtl93xx_pcs_validate(struct phylink_pcs *pcs,
405-
unsigned long *supported,
406-
const struct phylink_link_state *state)
407-
{
408-
struct rtl838x_pcs *rtpcs = container_of(pcs, struct rtl838x_pcs, pcs);
409-
struct rtl838x_switch_priv *priv = rtpcs->priv;
410-
int port = rtpcs->port;
411-
__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
412-
413-
pr_debug("In %s port %d, state is %d (%s)", __func__, port, state->interface,
414-
phy_modes(state->interface));
415-
416-
if (!phy_interface_mode_is_rgmii(state->interface) &&
417-
state->interface != PHY_INTERFACE_MODE_NA &&
418-
state->interface != PHY_INTERFACE_MODE_1000BASEX &&
419-
state->interface != PHY_INTERFACE_MODE_MII &&
420-
state->interface != PHY_INTERFACE_MODE_REVMII &&
421-
state->interface != PHY_INTERFACE_MODE_GMII &&
422-
state->interface != PHY_INTERFACE_MODE_QSGMII &&
423-
state->interface != PHY_INTERFACE_MODE_XGMII &&
424-
state->interface != PHY_INTERFACE_MODE_HSGMII &&
425-
state->interface != PHY_INTERFACE_MODE_10GBASER &&
426-
state->interface != PHY_INTERFACE_MODE_10GKR &&
427-
state->interface != PHY_INTERFACE_MODE_USXGMII &&
428-
state->interface != PHY_INTERFACE_MODE_INTERNAL &&
429-
state->interface != PHY_INTERFACE_MODE_SGMII) {
430-
bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
431-
dev_err(priv->ds->dev,
432-
"Unsupported interface: %d for port %d\n",
433-
state->interface, port);
434-
return -EINVAL;
435-
}
436-
437-
/* Allow all the expected bits */
438-
phylink_set(mask, Autoneg);
439-
phylink_set_port_modes(mask);
440-
phylink_set(mask, Pause);
441-
phylink_set(mask, Asym_Pause);
442-
443-
/* With the exclusion of MII and Reverse MII, we support Gigabit,
444-
* including Half duplex
445-
*/
446-
if (state->interface != PHY_INTERFACE_MODE_MII &&
447-
state->interface != PHY_INTERFACE_MODE_REVMII) {
448-
phylink_set(mask, 1000baseT_Full);
449-
phylink_set(mask, 1000baseT_Half);
450-
}
451-
452-
/* Internal phys of the RTL93xx family provide 10G */
453-
if (priv->ports[port].phy_is_integrated &&
454-
state->interface == PHY_INTERFACE_MODE_1000BASEX) {
455-
phylink_set(mask, 1000baseX_Full);
456-
} else if (priv->ports[port].phy_is_integrated) {
457-
phylink_set(mask, 1000baseX_Full);
458-
phylink_set(mask, 10000baseKR_Full);
459-
phylink_set(mask, 10000baseSR_Full);
460-
phylink_set(mask, 10000baseCR_Full);
461-
}
462-
if (state->interface == PHY_INTERFACE_MODE_INTERNAL) {
463-
phylink_set(mask, 1000baseX_Full);
464-
phylink_set(mask, 1000baseT_Full);
465-
phylink_set(mask, 10000baseKR_Full);
466-
phylink_set(mask, 10000baseT_Full);
467-
phylink_set(mask, 10000baseSR_Full);
468-
phylink_set(mask, 10000baseCR_Full);
469-
}
470-
471-
if (state->interface == PHY_INTERFACE_MODE_USXGMII) {
472-
phylink_set(mask, 2500baseT_Full);
473-
phylink_set(mask, 5000baseT_Full);
474-
phylink_set(mask, 10000baseT_Full);
475-
}
476-
477-
phylink_set(mask, 10baseT_Half);
478-
phylink_set(mask, 10baseT_Full);
479-
phylink_set(mask, 100baseT_Half);
480-
phylink_set(mask, 100baseT_Full);
481-
482-
bitmap_and(supported, supported, mask,
483-
__ETHTOOL_LINK_MODE_MASK_NBITS);
484-
pr_debug("%s leaving supported: %*pb", __func__, __ETHTOOL_LINK_MODE_MASK_NBITS, supported);
485-
486-
return 0;
487-
}
488-
489343
static void rtl83xx_pcs_get_state(struct phylink_pcs *pcs,
490344
struct phylink_link_state *state)
491345
{
@@ -680,8 +534,8 @@ static void rtl83xx_config_interface(int port, phy_interface_t interface)
680534
pr_debug("configured port %d for interface %s\n", port, phy_modes(interface));
681535
}
682536

683-
static void rtl83xx_phylink_get_caps(struct dsa_switch *ds, int port,
684-
struct phylink_config *config)
537+
static void rtldsa_phylink_get_caps(struct dsa_switch *ds, int port,
538+
struct phylink_config *config)
685539
{
686540
/*
687541
* TODO: This capability check will need some love. Depending on the model and the
@@ -692,14 +546,14 @@ static void rtl83xx_phylink_get_caps(struct dsa_switch *ds, int port,
692546
config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | MAC_10 | MAC_100 |
693547
MAC_1000FD | MAC_2500FD | MAC_5000FD | MAC_10000FD;
694548

549+
__set_bit(PHY_INTERFACE_MODE_1000BASEX, config->supported_interfaces);
550+
__set_bit(PHY_INTERFACE_MODE_10GBASER, config->supported_interfaces);
551+
__set_bit(PHY_INTERFACE_MODE_2500BASEX, config->supported_interfaces);
695552
__set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces);
696553
__set_bit(PHY_INTERFACE_MODE_INTERNAL, config->supported_interfaces);
697554
__set_bit(PHY_INTERFACE_MODE_QSGMII, config->supported_interfaces);
698555
__set_bit(PHY_INTERFACE_MODE_SGMII, config->supported_interfaces);
699556
__set_bit(PHY_INTERFACE_MODE_USXGMII, config->supported_interfaces);
700-
__set_bit(PHY_INTERFACE_MODE_XGMII, config->supported_interfaces);
701-
__set_bit(PHY_INTERFACE_MODE_1000BASEX, config->supported_interfaces);
702-
__set_bit(PHY_INTERFACE_MODE_10GBASER, config->supported_interfaces);
703557
}
704558

705559
static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
@@ -2191,7 +2045,6 @@ static int rtl83xx_dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_re
21912045

21922046
const struct phylink_pcs_ops rtl83xx_pcs_ops = {
21932047
.pcs_an_restart = rtl83xx_pcs_an_restart,
2194-
.pcs_validate = rtl83xx_pcs_validate,
21952048
.pcs_get_state = rtl83xx_pcs_get_state,
21962049
.pcs_config = rtl83xx_pcs_config,
21972050
};
@@ -2203,7 +2056,7 @@ const struct dsa_switch_ops rtl83xx_switch_ops = {
22032056
.phy_read = rtl83xx_dsa_phy_read,
22042057
.phy_write = rtl83xx_dsa_phy_write,
22052058

2206-
.phylink_get_caps = rtl83xx_phylink_get_caps,
2059+
.phylink_get_caps = rtldsa_phylink_get_caps,
22072060
.phylink_mac_config = rtl83xx_phylink_mac_config,
22082061
.phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
22092062
.phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
@@ -2249,7 +2102,6 @@ const struct dsa_switch_ops rtl83xx_switch_ops = {
22492102

22502103
const struct phylink_pcs_ops rtl93xx_pcs_ops = {
22512104
.pcs_an_restart = rtl83xx_pcs_an_restart,
2252-
.pcs_validate = rtl93xx_pcs_validate,
22532105
.pcs_get_state = rtl93xx_pcs_get_state,
22542106
.pcs_config = rtl83xx_pcs_config,
22552107
};
@@ -2261,7 +2113,7 @@ const struct dsa_switch_ops rtl930x_switch_ops = {
22612113
.phy_read = rtl83xx_dsa_phy_read,
22622114
.phy_write = rtl83xx_dsa_phy_write,
22632115

2264-
.phylink_get_caps = rtl83xx_phylink_get_caps,
2116+
.phylink_get_caps = rtldsa_phylink_get_caps,
22652117
.phylink_mac_config = rtl93xx_phylink_mac_config,
22662118
.phylink_mac_link_down = rtl93xx_phylink_mac_link_down,
22672119
.phylink_mac_link_up = rtl93xx_phylink_mac_link_up,

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