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plappermaulhauke
plappermaul
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hauke
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realtek: ethernet: switch to new family_id location
family_id is now part of the register set and automatically assigned during initialization. Make use of it. This is basically a conversion from priv->family_id to priv->r->family_id. While we are here convert some hard coded family ids to their proper defines. Signed-off-by: Markus Stockhausen <[email protected]> Link: openwrt/openwrt#21183 Signed-off-by: Hauke Mehrtens <[email protected]>
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  • target/linux/realtek/files-6.12/drivers/net/ethernet

1 file changed

+33
-35
lines changed

‎target/linux/realtek/files-6.12/drivers/net/ethernet/rtl838x_eth.c‎

Lines changed: 33 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -194,7 +194,6 @@ struct rtl838x_eth_priv {
194194
struct phylink_config phylink_config;
195195
struct phylink_pcs pcs;
196196
u16 id;
197-
u16 family_id;
198197
const struct rtl838x_eth_reg *r;
199198
u8 cpu_port;
200199
u32 lastEvent;
@@ -568,12 +567,12 @@ static void rtl838x_hw_reset(struct rtl838x_eth_priv *priv)
568567
u32 int_saved, nbuf;
569568
u32 reset_mask;
570569

571-
pr_info("RESETTING %x, CPU_PORT %d\n", priv->family_id, priv->cpu_port);
570+
pr_info("RESETTING %x, CPU_PORT %d\n", priv->r->family_id, priv->cpu_port);
572571
sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(priv->cpu_port));
573572
mdelay(100);
574573

575574
/* Disable and clear interrupts */
576-
if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) {
575+
if (priv->r->family_id == RTL9300_FAMILY_ID || priv->r->family_id == RTL9310_FAMILY_ID) {
577576
sw_w32(0x00000000, priv->r->dma_if_intr_rx_runout_msk);
578577
sw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_sts);
579578
sw_w32(0x00000000, priv->r->dma_if_intr_rx_done_msk);
@@ -585,7 +584,7 @@ static void rtl838x_hw_reset(struct rtl838x_eth_priv *priv)
585584
sw_w32(0xffffffff, priv->r->dma_if_intr_sts);
586585
}
587586

588-
if (priv->family_id == RTL8390_FAMILY_ID) {
587+
if (priv->r->family_id == RTL8390_FAMILY_ID) {
589588
/* Preserve L2 notification and NBUF settings */
590589
int_saved = sw_r32(priv->r->dma_if_intr_msk);
591590
nbuf = sw_r32(RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
@@ -599,7 +598,7 @@ static void rtl838x_hw_reset(struct rtl838x_eth_priv *priv)
599598
}
600599

601600
/* Reset NIC (SW_NIC_RST) and queues (SW_Q_RST) */
602-
if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID)
601+
if (priv->r->family_id == RTL9300_FAMILY_ID || priv->r->family_id == RTL9310_FAMILY_ID)
603602
reset_mask = 0x6;
604603
else
605604
reset_mask = 0xc;
@@ -612,11 +611,11 @@ static void rtl838x_hw_reset(struct rtl838x_eth_priv *priv)
612611
mdelay(100);
613612

614613
/* Setup Head of Line */
615-
if (priv->family_id == RTL8380_FAMILY_ID)
614+
if (priv->r->family_id == RTL8380_FAMILY_ID)
616615
sw_w32(0, RTL838X_DMA_IF_RX_RING_SIZE); /* Disabled on RTL8380 */
617-
if (priv->family_id == RTL8390_FAMILY_ID)
616+
if (priv->r->family_id == RTL8390_FAMILY_ID)
618617
sw_w32(0xffffffff, RTL839X_DMA_IF_RX_RING_CNTR);
619-
if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) {
618+
if (priv->r->family_id == RTL9300_FAMILY_ID || priv->r->family_id == RTL9310_FAMILY_ID) {
620619
for (int i = 0; i < priv->rxrings; i++) {
621620
int pos = (i % 3) * 10;
622621

@@ -627,7 +626,7 @@ static void rtl838x_hw_reset(struct rtl838x_eth_priv *priv)
627626
}
628627

629628
/* Re-enable link change interrupt */
630-
if (priv->family_id == RTL8390_FAMILY_ID) {
629+
if (priv->r->family_id == RTL8390_FAMILY_ID) {
631630
sw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG);
632631
sw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG + 4);
633632
sw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG);
@@ -729,12 +728,12 @@ static void rtl93xx_hw_en_rxtx(struct rtl838x_eth_priv *priv)
729728
/* Restart TX/RX to CPU port, enable CRC checking */
730729
sw_w32_mask(0x0, 0x3 | BIT(4), priv->r->mac_port_ctrl(priv->cpu_port));
731730

732-
if (priv->family_id == RTL9300_FAMILY_ID)
731+
if (priv->r->family_id == RTL9300_FAMILY_ID)
733732
sw_w32_mask(0, BIT(priv->cpu_port), RTL930X_L2_UNKN_UC_FLD_PMSK);
734733
else
735734
sw_w32_mask(0, BIT(priv->cpu_port), RTL931X_L2_UNKN_UC_FLD_PMSK);
736735

737-
if (priv->family_id == RTL9300_FAMILY_ID)
736+
if (priv->r->family_id == RTL9300_FAMILY_ID)
738737
sw_w32(0x217, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
739738
else
740739
sw_w32(0x2a1d, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
@@ -811,7 +810,7 @@ static int rtl838x_eth_open(struct net_device *ndev)
811810
spin_lock_irqsave(&priv->lock, flags);
812811
rtl838x_hw_reset(priv);
813812
rtl838x_setup_ring_buffer(priv, ring);
814-
if (priv->family_id == RTL8390_FAMILY_ID) {
813+
if (priv->r->family_id == RTL8390_FAMILY_ID) {
815814
rtl839x_setup_notify_ring_buffer(priv);
816815
/* Make sure the ring structure is visible to the ASIC */
817816
mb();
@@ -824,7 +823,7 @@ static int rtl838x_eth_open(struct net_device *ndev)
824823
for (int i = 0; i < priv->rxrings; i++)
825824
napi_enable(&priv->rx_qs[i].napi);
826825

827-
switch (priv->family_id) {
826+
switch (priv->r->family_id) {
828827
case RTL8380_FAMILY_ID:
829828
rtl838x_hw_en_rxtx(priv);
830829
/* Trap IGMP/MLD traffic to CPU-Port */
@@ -869,35 +868,35 @@ static int rtl838x_eth_open(struct net_device *ndev)
869868

870869
static void rtl838x_hw_stop(struct rtl838x_eth_priv *priv)
871870
{
872-
u32 force_mac = priv->family_id == RTL8380_FAMILY_ID ? 0x6192C : 0x75;
873-
u32 clear_irq = priv->family_id == RTL8380_FAMILY_ID ? 0x000fffff : 0x007fffff;
871+
u32 force_mac = priv->r->family_id == RTL8380_FAMILY_ID ? 0x6192C : 0x75;
872+
u32 clear_irq = priv->r->family_id == RTL8380_FAMILY_ID ? 0x000fffff : 0x007fffff;
874873

875874
/* Disable RX/TX from/to CPU-port */
876875
sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(priv->cpu_port));
877876

878877
/* Disable traffic */
879-
if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID)
878+
if (priv->r->family_id == RTL9300_FAMILY_ID || priv->r->family_id == RTL9310_FAMILY_ID)
880879
sw_w32_mask(RX_EN_93XX | TX_EN_93XX, 0, priv->r->dma_if_ctrl);
881880
else
882881
sw_w32_mask(RX_EN | TX_EN, 0, priv->r->dma_if_ctrl);
883882
mdelay(200); /* Test, whether this is needed */
884883

885884
/* Block all ports */
886-
if (priv->family_id == RTL8380_FAMILY_ID) {
885+
if (priv->r->family_id == RTL8380_FAMILY_ID) {
887886
sw_w32(0x03000000, RTL838X_TBL_ACCESS_DATA_0(0));
888887
sw_w32(0x00000000, RTL838X_TBL_ACCESS_DATA_0(1));
889888
sw_w32(1 << 15 | 2 << 12, RTL838X_TBL_ACCESS_CTRL_0);
890889
}
891890

892891
/* Flush L2 address cache */
893-
if (priv->family_id == RTL8380_FAMILY_ID) {
892+
if (priv->r->family_id == RTL8380_FAMILY_ID) {
894893
/* Disable FAST_AGE_OUT otherwise flush will hang */
895894
sw_w32_mask(BIT(23), 0, RTL838X_L2_CTRL_1);
896895
for (int i = 0; i <= priv->cpu_port; i++) {
897896
sw_w32(BIT(26) | BIT(23) | i << 5, priv->r->l2_tbl_flush_ctrl);
898897
do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26));
899898
}
900-
} else if (priv->family_id == RTL8390_FAMILY_ID) {
899+
} else if (priv->r->family_id == RTL8390_FAMILY_ID) {
901900
for (int i = 0; i <= priv->cpu_port; i++) {
902901
sw_w32(BIT(28) | BIT(25) | i << 5, priv->r->l2_tbl_flush_ctrl);
903902
do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(28));
@@ -906,16 +905,16 @@ static void rtl838x_hw_stop(struct rtl838x_eth_priv *priv)
906905
/* TODO: L2 flush register is 64 bit on RTL931X and 930X */
907906

908907
/* CPU-Port: Link down */
909-
if (priv->family_id == RTL8380_FAMILY_ID || priv->family_id == RTL8390_FAMILY_ID)
908+
if (priv->r->family_id == RTL8380_FAMILY_ID || priv->r->family_id == RTL8390_FAMILY_ID)
910909
sw_w32(force_mac, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
911-
else if (priv->family_id == RTL9300_FAMILY_ID)
910+
else if (priv->r->family_id == RTL9300_FAMILY_ID)
912911
sw_w32_mask(0x3, 0, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
913-
else if (priv->family_id == RTL9310_FAMILY_ID)
912+
else if (priv->r->family_id == RTL9310_FAMILY_ID)
914913
sw_w32_mask(BIT(0) | BIT(9), 0, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
915914
mdelay(100);
916915

917916
/* Disable all TX/RX interrupts */
918-
if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) {
917+
if (priv->r->family_id == RTL9300_FAMILY_ID || priv->r->family_id == RTL9310_FAMILY_ID) {
919918
sw_w32(0x00000000, priv->r->dma_if_intr_rx_runout_msk);
920919
sw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_sts);
921920
sw_w32(0x00000000, priv->r->dma_if_intr_rx_done_msk);
@@ -1086,7 +1085,7 @@ static int rtl838x_eth_tx(struct sk_buff *skb, struct net_device *dev)
10861085
h->size = len;
10871086
h->len = len;
10881087
/* On RTL8380 SoCs, small packet lengths being sent need adjustments */
1089-
if (priv->family_id == RTL8380_FAMILY_ID) {
1088+
if (priv->r->family_id == RTL8380_FAMILY_ID) {
10901089
if (len < ETH_ZLEN - 4)
10911090
h->len -= 4;
10921091
}
@@ -1103,7 +1102,7 @@ static int rtl838x_eth_tx(struct sk_buff *skb, struct net_device *dev)
11031102
ring->tx_r[q][ring->c_tx[q]] |= 1;
11041103

11051104
/* Before starting TX, prevent a Lextra bus bug on RTL8380 SoCs */
1106-
if (priv->family_id == RTL8380_FAMILY_ID) {
1105+
if (priv->r->family_id == RTL8380_FAMILY_ID) {
11071106
for (int i = 0; i < 10; i++) {
11081107
u32 val = sw_r32(priv->r->dma_if_ctrl);
11091108

@@ -1113,7 +1112,7 @@ static int rtl838x_eth_tx(struct sk_buff *skb, struct net_device *dev)
11131112
}
11141113

11151114
/* Tell switch to send data */
1116-
if (priv->family_id == RTL9310_FAMILY_ID || priv->family_id == RTL9300_FAMILY_ID) {
1115+
if (priv->r->family_id == RTL9310_FAMILY_ID || priv->r->family_id == RTL9300_FAMILY_ID) {
11171116
/* Ring ID q == 0: Low priority, Ring ID = 1: High prio queue */
11181117
if (!q)
11191118
sw_w32_mask(0, BIT(2), priv->r->dma_if_ctrl);
@@ -1205,7 +1204,7 @@ static int rtl838x_hw_receive(struct net_device *dev, int r, int budget)
12051204
skb = netdev_alloc_skb_ip_align(dev, len);
12061205
if (likely(skb)) {
12071206
/* BUG: Prevent bug on RTL838x SoCs */
1208-
if (priv->family_id == RTL8380_FAMILY_ID) {
1207+
if (priv->r->family_id == RTL8380_FAMILY_ID) {
12091208
sw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0));
12101209
for (int i = 0; i < priv->rxrings; i++) {
12111210
unsigned int val;
@@ -1290,7 +1289,7 @@ static int rtl838x_poll_rx(struct napi_struct *napi, int budget)
12901289
if (work_done < budget && napi_complete_done(napi, work_done)) {
12911290
/* Re-enable rx interrupts */
12921291
spin_lock_irqsave(&priv->lock, flags);
1293-
if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID)
1292+
if (priv->r->family_id == RTL9300_FAMILY_ID || priv->r->family_id == RTL9310_FAMILY_ID)
12941293
sw_w32_mask(0, RTL93XX_DMA_IF_INTR_RX_MASK(ring), priv->r->dma_if_intr_rx_done_msk);
12951294
else
12961295
sw_w32_mask(0, RTL83XX_DMA_IF_INTR_RX_MASK(ring), priv->r->dma_if_intr_msk);
@@ -1316,7 +1315,7 @@ static void rtl838x_pcs_an_restart(struct phylink_pcs *pcs)
13161315
struct rtl838x_eth_priv *priv = container_of(pcs, struct rtl838x_eth_priv, pcs);
13171316

13181317
/* This works only on RTL838x chips */
1319-
if (priv->family_id != RTL8380_FAMILY_ID)
1318+
if (priv->r->family_id != RTL8380_FAMILY_ID)
13201319
return;
13211320

13221321
pr_debug("In %s\n", __func__);
@@ -1414,7 +1413,7 @@ static void rtl838x_set_mac_hw(struct net_device *dev, u8 *mac)
14141413
sw_w32((mac[0] << 8) | mac[1], priv->r->mac);
14151414
sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], priv->r->mac + 4);
14161415

1417-
if (priv->family_id == RTL8380_FAMILY_ID) {
1416+
if (priv->r->family_id == RTL8380_FAMILY_ID) {
14181417
/* 2 more registers, ALE/MAC block */
14191418
sw_w32((mac[0] << 8) | mac[1], RTL838X_MAC_ALE);
14201419
sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
@@ -1452,11 +1451,11 @@ static int rtl8390_init_mac(struct rtl838x_eth_priv *priv)
14521451

14531452
static int rtl8380_init_mac(struct rtl838x_eth_priv *priv)
14541453
{
1455-
if (priv->family_id == 0x8390)
1454+
if (priv->r->family_id == RTL8390_FAMILY_ID)
14561455
return rtl8390_init_mac(priv);
14571456

14581457
/* At present we do not know how to set up EEE on any other SoC than RTL8380 */
1459-
if (priv->family_id != 0x8380)
1458+
if (priv->r->family_id != RTL8380_FAMILY_ID)
14601459
return 0;
14611460

14621461
pr_info("%s\n", __func__);
@@ -1703,16 +1702,15 @@ static int __init rtl838x_eth_probe(struct platform_device *pdev)
17031702
dev->hw_features = NETIF_F_RXCSUM;
17041703

17051704
priv->id = soc_info.id;
1706-
priv->family_id = soc_info.family;
17071705
if (priv->id) {
17081706
pr_info("Found SoC ID: %4x: %s, family %x\n",
1709-
priv->id, soc_info.name, priv->family_id);
1707+
priv->id, soc_info.name, priv->r->family_id);
17101708
} else {
17111709
pr_err("Unknown chip id (%04x)\n", priv->id);
17121710
return -ENODEV;
17131711
}
17141712

1715-
switch (priv->family_id) {
1713+
switch (priv->r->family_id) {
17161714
case RTL8380_FAMILY_ID:
17171715
priv->cpu_port = RTL838X_CPU_PORT;
17181716
dev->netdev_ops = &rtl838x_eth_netdev_ops;

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